DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are present for examination.
The summitted IDS filed on 12/10/24 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-8 & 14-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pitner et al (US 2022/0392552).
` Claims 1, 4, 8. 14 & 20, Pitner et al (see Figs. 12A-12B) shows a memory structure comprising a cell array 300 with a plurality of blocks together with associated circuitry such as memory controller, sense amplifiers, and read/write voltages, etc., for handling their read/write operations by selecting each block with a multiplexer and enabling the respective address decoders with WL voltages for programming and verifying purposes, etc.
Furthermore, Fig. 18 shows the method steps of performing a program-verify operation that uses verifies only one string according to a “bit-scan configuration” for the entire block(see also Fig. 17). Particularly, after the program loop (i.e., steps 1200-1206b) all the cell strings, or a set of strings, inside a block are programed, then comes the single step 1206a for selecting a particular string out of a partial bit scan configuration, which is also less than all the sets of strings as claimed, for verifying that only selected string and finally decide in step 1208 if the whole memory block is already passed (step 1210a) or already failed (step 1210b). Para [0087] also stated the goal of this verify approach is to only verify “the memory cells of the selected bit lines” during the program-verify operation so to save or reduce the program-verify time for the whole block. Thus, by verifying this way, these memory strings chosen for verified are also less than all the set of memory strings (in a block) as claimed. See below:
PNG
media_image1.png
394
928
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Greyscale
[AltContent: textbox (Last step of deciding if the whole
cell block is passed or failed
status?)][AltContent: arrow][AltContent: arrow][AltContent: textbox (Second step of verifying only the number
of selected strings (selected by partial scan),
which is also less than all the strings of
in the whole set, to reduce program/verify time
of strings)][AltContent: arrow][AltContent: textbox (First step of programming a set
of strings in a memory block
steps 1200- to 1206b)]
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628
532
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Greyscale
Claims 2 & 15, step 1208 of the method chart above will also determine if a number of failed cells is less than all the strings in the set, and further decide if the whole program operation is succeed of failed as well.
Claims 3-4 & 16-17, Fig. 16 shows “four program pulses” are needs but only “one verify pulse 910” applied to one WL string is needed to verify the whole block as shown in Fig. 17; thus, the number of verify pulses are less than the total number of program pulses, which will shorten the total time during the program-verify operation as claimed.
Claims 5 & 18, the step 1206a, as shown in Fig. 18 above, will also identify and select one or more particular bit line strings based on a “partial bit scan operation”, and will only apply one or more program-verify voltage pulses to one or more such slected memory strings as claimed.
Claims 6 & 19, Fig. 15 shows three configurations, where only one out of 16 cells of a string is selected for verifying in a tiered or page scan configurations, and each such configuration data is also stored in register and used by the controller circuitry (115, Fig. 1) as a conventional techniques well-known to a skilled person in this art.
Claim 7, Fig. 18 also shows the program-verify pulse is performed in step 1208, which is immediately followed the first program pulse carried out in step 1202.
Claim 8, single level cells (or SLC) is shown in Figs. 5 & 17.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 & 14, line 2, the term ‘each of a set”, in singular form, is vague and indefinite because there is only “one set” claimed; thus, the term “each” might imply there are more than one set is being claimed already? Similarly, line 4, the term “all the set”, in singular form, is also vague and indefinite. If this implies “all the strings of a set in a memory block”, see line 2-3, then it should say so for the sake of claim clarity.
Claims 2-5, 7, 12, 15-18 & 20 also contain the similar terms “ all the set” as discussed above.
Claims 9-11 also contain similar terms “each of the set” (in singular form) as discussed above.
Claims 6, 8, 13 and 19 are tentatively rejected for dependent upon their rejected parent claims 1, 14 or 20, respectively.
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827