DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in present Application filed on December 16, 2024.
Information Disclosure Statement
The information disclosure statements filed August 07,2024 and January 13,2025 have been submitted for consideration by the Office. It has been placed in the application file and the information referred to therein has been considered.
Applicants must continue to submit prior art references throughout the patent application process. A supplemental IDS must be submitted if prior art is discovered through a foreign patent application or an International Patent Search, or a related application before a prosecution closes.
Election/Restriction
Applicant’s election without traverse of Invention I and species A3, encompassing claims 1-11 in the reply filed on July 28, 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Rejection of claim 5, the limitation “a ground via conductor penetrating through the first dielectric layer, wherein the ground via conductor is separated from the isolation layer, wherein the ground via hole connects a second portion of the signal layer to the ground portion of the inner wiring layers” is unclear or indefinite.
Note that a ground via hole conductor connects a second portion of the signal layer to the ground portion of the inner wiring layers not a ground via hole.
Appropriate correction is required.
Rejection of claims 6-7, claim 6 is rejected for the same reason applied to rejection of claim 5 above.
Rejection of claim 7, the limitation “a second filler dielectric material in the ground via hole” is indefinite because it lacks essential structure.
The ground via
Appropriate correction is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AlA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102 which forms the basis for all rejections set forth in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 and 10 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) (whichever apply) as being anticipated by Cheng et al. (US6353999, herein referred to as Chen) or Young et al. (US20100156997, herein referred to Young), or Caletka et al. (US20070289773, herein referred to as Caletka).
Rejection of claim 1, Cheng (figures 6 of Cheng) or Young (figure 5 of Young) or Caletka (figure 9 or 11 of Caletka) a circuit board structure, comprising:
a composite layer (216 of Cheng; see middle composite substrate with multiple insulating and conductive layers at 211 separated by 213) comprising a plurality of dielectric layers (200 of Cheng) and a plurality of inner wiring layers (202C-Dof Cheng) disposed on surfaces of the dielectric layers;
a first dielectric layer (a bottom 214 layer of Cheng; or a bottom 213 layer of Young) on a bottom surface of the composite layer;
a second dielectric layer (a top 214 layer of Cheng; or a top 213 layer of Young) on a top surface of the composite layer;
a isolation layer (a middle 214 layer in Cheng; or a middle 213 layer of Young) between the first dielectric layer and the second dielectric layer, and adjacent to the composite layer,
wherein the isolation layer, the first dielectric layer and the second dielectric layer jointly have an opening extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer (see opening 206 extending from top to bottom in Cheng; see opening extending top to bottom in Young);
a first conductive layer (204 of Cheng; see outer via conductor of Young) between the isolation layer and the inner wiring layers, and connected to a ground portion of the inner wiring layers (end of 202C-D of Cheng; see conductors horizontally connected to the outer via conductor in Young);
a second conductive layer (208 of Cheng; or inner via conductor of Young) covering an inner well of the opening (208 of Cheng; or see opening of Young), wherein the isolation layer separates the second conductive layer from the first conductive layer, and the second conductive layer, the isolation layer and the first conductive layer form a coaxial via (see figure 6 of Cheng; see figure 5 of Young);
an antenna layer (202a of Cheng; or top conductor 215 and/or 217 of Young) above the top surface of the second dielectric layer, wherein the antenna layer is connected to a top end of the second conductive layer; and
a signal layer (202f of Cheng; or bottom conductor 215 and/or 217 of Young) below the bottom surface of the first dielectric layer, wherein a first portion of the signal layer is connected to a bottom end of the second conductive layer (similarly Caletka discloses the claim structure).
Rejection of claim 2, Cheng or Caletka discloses the circuit board structure of claim 1, further comprising: a first filler dielectric material in the opening (Cheng states A micro via, which is to be filled with insulating material to form a plug 206; or 73 in Caletka).
Rejection of claim 3, Cheng or Caletka discloses the circuit board structure of claim 2, wherein a top surface of the first filler dielectric material is higher than the top surface of the second dielectric layer, and a bottom surface of the first filler dielectric material is lower than the bottom surface of the first dielectric layer (see top surfaces of plug 206 in figure 6 of Cheng; see top surfaces of plug 73 in the figures of Caletka).
Rejection of claim 4, Caletka discloses the circuit board structure of claim 2, wherein the antenna layer covers a top surface of the first filler dielectric material, and the signal layer covers a bottom surface of the first filler dielectric material (see 71 in figure 11 of Caletka).
Rejection of claim 5, Young discloses the circuit board structure of claim 1, further comprising: a ground via conductor penetrating through the first dielectric layer, wherein the ground via conductor is separated from the isolation layer, wherein the ground via conductor connects a second portion of the signal layer to the ground portion of the inner wiring layers (see at 215b of signal layer connected a ground via penetrating through bottom layer 213 and connected to inner wiring layers) .
Rejection of claim 6, Young discloses the circuit board structure of claim 5, wherein the isolation layer has a first sidewall and a second sidewall opposite each other, the first sidewall of the isolation layer is in contact with the second conductive layer, and the second sidewall of the isolation layer is in contact with the ground portion of the inner wiring layers (see figure wherein middle 213 contacts the second conductive layer and with the inner wiring layers).
Rejection of claim 10, Cheng discloses the circuit board structure of claim 1, wherein the antenna layer has an antenna line, and the antenna line overlaps the coaxial via ( a line shape of 202a over part of coaxial via of Cheng).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over by Young and Oggioni et al. (US20040069529, herein referred to as Oggioni) or Lee et al. (US20020184757, herein referred to as Lee).
Rejection of claim 7, Young discloses the circuit board structure of claim 1, but fails to disclose but further comprising: a second filler dielectric material in an inner opening portion of the ground via hole.
Oggioni or Lee disclose but further comprising: a second filler dielectric material in an inner opening portion of the ground via hole (see V shaped via conductor with insulating material inner surface of V-shaped via conductor in figure 4 of Oggioni; or see figures 4-5 of Lee wherein insulating material filled in the via conductor. ).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit structure to have via structure as taught by Oggioni or Lee so that resin fills prevent collapse during lamination and reduce voids from trapped gas or moisture, and /or reduces thermal stress differences between copper and surrounding dielectric, improves impedance control, or minimizes signal degradation.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over by Cheng, Young, or Caletka and in view of Wu et al. (US20170231083, herein referred to as Wu).
Rejection of claim 8, Cheng, Young, or Caletka discloses the circuit board structure of claim 1 but fails to disclose a dielectric constant of the isolation layer is lower than a dielectric constant of the dielectric layers.
Wu disclose wherein a dielectric constant of the isolation layer is lower than a dielectric constant of the dielectric layers (the dielectric material 12 on one side of first conductive layer has a dielectric constant smaller than a dielectric constant of the substrate material 10 of first conductive layer across inner layers, see paragraph 0039 of Wu; and the dielectric constant of the dielectric block 12 can be in a range from about 1 to about 4. The dielectric constant of PI is in a range from about 3 to about 4).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit structure to have structure as taught by Wu so that he low-k dielectric material reduces parasitic capacitance between the conductors 14, enabling faster switching speeds and lower electronic crosstalk. That is, the low-k dielectric block 12 can enhance signal isolation between the conductors 14 as well as the low-k dielectric block 12 can lower the capacitance of the conductive lines 18.
Rejection of claim 9, Cheng, Young, or Caletka in view of Wu discloses the circuit board structure of claim 8, wherein the dielectric constant of the isolation layer is between 3 and 3.5 (see rejection of claim 8 above).
Rejection of claim 10, Cheng, Young, or Caletka in view of Wu discloses the circuit board structure of claim 1, wherein the antenna layer has an antenna line, and the antenna line overlaps the coaxial via (see line shape 18 and explanation in rejection of claim 8 above, additionally se Wu).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over by Cheng Young or Caletka and in view of Luo et al. (US20200076051, herein referred to as Luo).
Rejection of claim 11, Cheng, Young, or Caletka in Wire of Wu discloses the circuit board structure of claim 1, but fails to disclose a wire on the top end of the second conductive layer, and configured to connect an antenna.
Luo discloses a wire on the top end of the second conductive layer, and configured to connect an antenna (one of 14A-14C; and a wire bond 14B (shown in dash) having a larger diameter may be used to connect the antenna structure 20 with the pad 13. The use of a larger or smaller diameter wire bond 14A, 14B enables the antenna configuration of the semiconductor device 100A to be tunable as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. And see figure 1 of Luo).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit board structure to have structure as taught by Luo so that a radio communication device electrically connected or communicate with the via pad structure of substrate via a wire, and the antenna or antenna configuration may be tuned to the requirements of the radio communication device. The antenna configuration may be tuned by connected to different antenna structures on the surface of the substrate. The antenna configuration may be tuned by changing a length of the wire bond, changing a diameter of the wire bond, and/or changing the material of the wire bond.
Pertinent Prior Arts
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. Please refer to the enclosed PTO-892 form for the citation of pertinent arts in the present case, all of which disclose circuit board structure.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARESH PAGHADAL whose telephone number is (571)272-5251. The examiner can normally be reached 7:00AM-4:00PM, Monday - Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PARESH PAGHADAL/ Primary Examiner, Art Unit 2847
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