DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on December 10, 2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 8, 2024, September 27, 2024, October 3, 2024 is being considered by the examiner.
Claim Objections
Claim 12 objected to because of the following informalities: lines: 11-12 recite the limitation “wherein the power component is a power transistor or as a diode” Examiner believes this is meant to read “or is a diode” and will be interpreted as such. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the functional layers" in lines: 7-8. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the one or more functional layers”
Claim 2 recites the limitation "already applied layers" in lines: 7-8. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the one or more functional layers”
Claim 5 recites the limitation "the second engineered layer" in lines: 2-3. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the at least one second engineered layer”
Claim 12 recites the limitation "the functional layers" in lines: 6-7. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the one or more functional layers”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Berger (US 2019/0244850). Claim 1, Berger discloses (Figs. 7A-7F) a method for producing a power component (Fig. 7F shows forming vertical power semiconductor, Para [0129]) based on a wide bandgap semiconductor (substrate 300 formed from SiC, GaN, GaAs, Para [0094]), the method comprising the following steps: providing (Fig. 7A) a device wafer with a substrate (300, auxiliary substrate, Para [0122]); forming (Fig. 7E) one or more functional layers (110, component layer, Para [0126]) on the substrate that form the power component (110 formed on 300 for vertical power semiconductor, Para [0129]); disposing (Fig. 7E) at least one engineered layer (250, separation layer, Para [0058]) between the one or more functional layers and the substrate (250 is between 110 and 300); completely removing (Figs. 7E-7F) the substrate from the device wafer by selectively removing at least one of the at least one engineered layer (300 is completely removed by also removing 250, Para [0127]). Claim 2, Berger discloses (Figs. 7A-7F) The method according to claim 1, wherein, prior to removal of the substrate (in Fig. 7F), the one or more functional layers (110) are stabilized by a carrier layer (900, wafer composite stabilizes 110 in Fig. 7E, Para [0127]), the carrier layer (900) including a carrier wafer (900 includes auxiliary carrier 400, Para [0127]). Claim 12, Berger discloses (Figs. 7A-7F) a power component (Fig. 7F shows forming vertical power semiconductor, Para [0129]) based on a wide bandgap semiconductor(substrate 300 formed from SiC, GaN, GaAs, Para [0094]) , wherein the power component is produced by (the following limitations are considered product-by-process and get little patentable weight): providing(Fig. 7A) a device wafer with a substrate (300, auxiliary substrate, Para [0122]); forming (Fig. 7E) one or more functional layers (110, component layer, Para [0126]) on the substrate that form the power component (110 formed on 300 for vertical power semiconductor, Para [0129]); disposing (Fig. 7E) at least one engineered layer (250, separation layer, Para [0058]) between the one or more functional layers and the substrate (250 is between 110 and 300); completely removing (Figs. 7E-7F) the substrate from the device wafer by selectively removing at least one of the at least one engineered layer (300 is completely removed by also removing 250, Para [0127]); wherein the power component is a power transistor or is a diode (Fig. 7F shows a vertical power semiconductor, Para [0129]). Claim 13, Berger discloses (Figs. 7A-7F) the power component according to Claim 12, wherein the power component includes GaN or GaO or SiC as functional semiconductor material (300 comprises GaN or SiC as a functional semiconductor material, Para [0062]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Berger (US 2019/0244850) as applied to claim 1 above, and further in view of Dallesasse (US 2022/0278073). Claim 4, Berger discloses (Figs. 7A-7F) the method according to claim 1, wherein at least one first engineered layer (252, support structure, Para [0065]) is formed as a silicon layer (252 can be silicon (polycrystalline silicon), Para [0073]) and the at least one first engineered layer is removed via an etching medium (252 is removed by a gas mixture, Para [0070] – [0071]). Berger does not explicitly disclose an etching medium including xenon difluoride gas. However, Dallesasse discloses a dry etching process for silicon using xenon difluoride (Para [0043]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize xenon difluoride of Dallesasse as the gas mixture for removing the silicon support structure of Berger as it a common mixture for silicon-based materials (Dallesasse, Para [0043]). Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Berger (US 2019/0244850) in view of Dallesasse (US 2022/0278073) as applied to claim 4 above, and further in view of Oda (US 2007/0178676). Claim 5, Berger in view of Dallesasse discloses the method according to claim 4. Berger discloses (Figs. 7a-7F) wherein at least one second engineered layer (255, sacrificial material, Para [0071]) is formed as a silicon oxide layer (255 may be silicon oxide, Para [ 0071]) and the at least one second engineered layer is removed via an etching medium (255 removed by gas mixture, Par a[0070] – [0071]). Berger in view of Dallesasse does explicitly disclose and etching medium including HF gas. However, Oda discloses HF gas can be used to etch silicon oxide (Para [0057]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the HF gas of Oda as the etching medium for removing the silicon oxide layer of Berger as it a common gas for etching silicon oxide material (Oda, Para [0057]).
Allowable Subject Matter
Claims 3 and 6-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Berger (US 2019/0244850), Dallesasse (US 2022/0278073), Oda (US 2007/0178676), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 3 (from which claims 6-11 depend), applying a passivation to a surface of the device wafer and side walls of the at least one trench; removing the passivation from a base of the at least one trench and forming a depression in the trench such that the at least one engineered layer is exposed…
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
Prosecution Insights