DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are presented for examination in this application. The application filing date on 08/08/2024. Claims 1, 11 and 20 are independent.
Examiner notes
(A). Drawings submitted on 08/08/2024 comply with the provisions of 37 CFR 1.121(d).
(B). Limitations have been provided with the Bold fonts in order to distinguish from the cited part of the reference (Italic).
(C). Examiner has cited particular columns, line numbers, references, or figures in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 VI and 2123.
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CF
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1, line 1, replace “circuitry to” with --circuitry configured to--”.
Claim 2, line 1, “insructions”, should be –instructions--.
Claims 3, 4, 5, 6, 8, and 9, line 2, replace “further to” with --further configured to--.
Claim 5, line 2, 4, “insructions”, should be –instructions--.
Claim 11, line 1, replace “processors to” with –processors configured to--.
Claims 12, 13, 15, 17, and 18, line 1, replace “further to” with --further configured to--.
Claim 20, line 2, replace “circuitry to” with --circuitry configured to--”.
These claims 7, 10, 14, 16, and 19 are dependent claims of objected claims and they inherit the same issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 3 and 10 are rejected under 35 U.S.C. 103 as being obvious over Bates et al. (US 20150309913 A1, hereinafter Bates) in view of Bates and Smith et al. (US 9612937 B2, hereinafter Smith).
As to claim 1, Bates discloses one or more processors comprising processing circuitry to:
generate, using a control flow graph representing a set of instructions corresponding to source code of a program (abstract, Computer program source code is represented by nodes in a control flow graph … . Further, par.0007, FIG. 1 depicts an example method for generating a variable initialization scorecard for computer program source code),
a first map that identifies one or more declared variables from the set of instructions and one or more variable definition instructions from the set of instructions (par. 0016, … The variables' scores may be determined [i.e. identify] by statically analyzing the source code using algorithms such as those described below. After the scorecard is generated, …);
update the first map based at least on propagation of an indication of the one or more variable definition instructions to one or more basic blocks of the control flow graph (abstract, …based on the modifications [i.e. update] to the variable that are defined by the lines of source code … . Further, par. 0004, …The set of new scores is based on the modifications [i.e. update] to the variable defined by the target lines … .);
evaluate one or more definition-use chains associated with the control flow graph based at least on a correlation of variable use instructions in the one or more definition-use chains with the one or more basic blocks based on the first map (par. 0012, …computer program source code analysis, and more particular aspects relate to evaluating the likelihood that a source code variable is uninitialized in a section of source code. …); and
Beats does not explicitly disclose the following limitations but,
Smith discloses generate an output representing a usage of one or more uninitialized variables in the set of instructions based on the correlation (col. 3, ll. 25, a declaration event that indicates an operation on a variable (e.g., an uninitialized variable, an integer variable value of zero); and a failed-assertion event that indicates a determined defect in the source code. Other types of events include a function event that indicates where a function call is initiated in the source code, and includes the input and/or output parameters of the function).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Bates to include generate an output representing a usage of one or more uninitialized variables in the set of instructions based on the correlation, as disclosed by Smith, for the purpose of identifying events include a function event that indicates where a function call is initiated in the source code, and includes the output parameters of the function. (see col. 3, ll. 28-31 of Smith).
As to claim 3, Smith discloses the one or more processors (col. 2, ll. 62-63, various components, such as a processor and/or memory system) wherein the one or more processors are further to generate a report comprising at least an indication of one or more portions of the program source code that use the one or more uninitialized variables (col. 3, ll. 16-76, the key event manager 104 is implemented to log events 110 [i.e. report] that occur during the static code analysis along the executable paths in the source code. In embodiments, the events are logged and used to determine events that are relevant to a user from the analysis. The events 110 can include different event types 112, such as an alias event that indicates at least two variables correspond to a same reference; a branch event that indicates a change of executable paths in the source code 102 (e.g., control flow switch changes); a declaration event that indicates an operation on a variable (e.g., an uninitialized variable), an integer variable value of zero).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Bates to include the one or more processors wherein the one or more processors are further to generate a report comprising at least an indication of one or more portions of the program source code that use the one or more uninitialized variables, as disclosed by Smith, for the purpose of identifying events include a function event that indicates where a function call is initiated in the source code, and includes the output parameters of the function. (see col. 3, ll. 28-31 of Smith)
As to claim 10, Smith discloses the one or more processors wherein the one or more processors are comprised in at least one of:
a system implemented at least partially using cloud computing resources (col. 6, ll. 34-40, The cloud 406 includes and/or is representative of the platform 408 for the networked service components (i.e., the key event manager, source code analysis, and the state machine) that implement embodiments of determining relevant events in source code analysis. The platform abstracts underlying functionality of hardware, such as server devices, and/or software resources of the cloud).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Bates to include a system implemented at least partially using cloud computing resources, as disclosed by Smith, for the purpose of interconnecting architecture enables functionality across multiple devices to provide a networked service environment of the multiple devices . (see col. 5, ll. 23-25 of Smith).
Claim 2 is rejected under 35 U.S.C. 103 as being obvious over Bates et al. and Smith et al. as applied to claim 1 in the above and further in view of Mcardle et al. (US 11669642 B1, hereinafter Mcardle).
As to claim 2, Bates as modified by Smith does not explicitly disclose the following limitation but,
Mcardle discloses the one or more processors, wherein the set of instructions comprise a static single assignment (SSA) intermediate representation (IR) of the program source code (col. 2, ll. 41-47, executing an application, a processor may access the application binary file from the disk and translate the application binary into intermediate representation. The intermediate representation may be code comprising an intermediate graph structure that allows for flow analysis. Further, col. 7, ll. 37-43, Static Single Assignment (SSA) representation. This property enables the processor to compute reaching definitions using LLVM-based analyses, such as MemorySSA, or other existing implementation. Reaching definitions is a data-flow analysis, which statically determines which definitions may reach a given point in the code).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Bates to include the one or more processors, wherein the set of instructions comprise a static single assignment (SSA) intermediate representation (IR) of the program source code, as disclosed by Mcardle, for the purpose of . (see col. 3, ll. 28-31 of Mcardle).
Claim 4 is rejected under 35 U.S.C. 103 as being obvious over Bates et al. and Smith et al. as applied to claims 1 in the above and further in view of Simhadri et al. (US 10191943 B2, hereinafter Simhadri).
As to claim 4, Bates discloses the one or more processors wherein the one or more processors are further to propagate the indication of the one or more variable definition instructions to the one or more basic blocks of the (par. 0018, FIG. 1 depicts an example method 100 for generating a variable initialization scorecard for computer program source code. The computer program is represented by a control flow graph. In the control flow graph, each node represents a basic block of source code. A basic block of source code is a straight-line code segment without any jumps or jump targets. In a control flow graph, jump targets start a block and jumps end a block. Jumps in the control flow are represented by directed edges between nodes).
Bates as modified by Smith does not disclose the following limitation but,
Simhadri discloses the one or more processors wherein the one or more processors are control flow graph based on a tree (Figs. 3, 4, the construction of the expression tree for the CFG. Further, col. 6, ll. 64-67, the expression tree corresponding to the else branch (i.e., p is false). This expressions (p, e.sub.t, e.sub.f) captures the contribution of the entire conditional block and hence the block can be logically seen as a single node in the CFG).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Bates to include the one or more processors wherein the one or more processors are control flow graph based on a tree, as disclosed by Simhadri, for the purpose of constructing of the expression tree for the CFG and expressions with their corresponding Apply operator types. (see col. 7, ll. 27-29 of Simhadri).
Claim 5 is rejected under 35 U.S.C. 103 as being obvious over Bates et al. and Smith et al. as applied to claim 1 in the above and further in view of Ng et al. (US 6202203 B1, hereinafter Ng).
As to claim 5, Bates as modified by Smith does not explicitly disclose the following limitation but,
Ng discloses the one or more processors wherein the one or more processors are further to compile the set of instructions into a machine-executable code based on the output representing the usage of one or more uninitialized variables indicating that the set of instructions does not include uninitialized variables (Figs. 1, 2, construction of the expression tree for the CFG. The expressions with their corresponding Apply operator types. Further, Fig. 4, col. 5, ll. 22-32, decision block 445, if none of the operand value numbers of the .phi.-function are equal to 1, then decision block 455 determines if there is an uninitialized or external variable. If there is an uninitialized or external variable, then process block 460 assigns a new value to the .phi.-function value number. Thereafter, decision block 465 determines if the definition of the operand is value numbered. If the definition of the operand is value numbered, then processing continues to decision block 440 to determine if there are remaining expressions in the basic block to be processed by the loop).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Bates to include the one or more processors wherein the one or more processors are further to compile the set of instructions into a machine-executable code based on the output representing the usage of one or more uninitialized variables indicating that the set of instructions does not include uninitialized variables, as disclosed by Ng, for the purpose of providing improved compilation optimization. (see col. 2, ll. 50-51 of Ng).
Claim 6 is rejected under 35 U.S.C. 103 as being obvious over Bates et al. and Smith et al. as applied to claim 1 in the above and further in view of Meyer et al. (US 20180143813 A1, hereinafter Meyer).
As to claim 6, Bates as modified by Smith does not explicitly disclose the following limitation but,
Meyer discloses the one or more processors (abstract, The compiler includes an interface component configured to load from a storage component program code to be executed by one or more processors) wherein the one or more processors are further to identify the one or more basic blocks of the control flow graph in the first map based at least on one or more basic block identifiers that uniquely identify individual basic blocks of the control flow graph (par. 0077, … configured to identify at least one data dependency between a first statement in a first basic block and a second statement in a second basic block where a data flow is indicated from a first processor (p1) to a second processor (p2) of the multi-processor system, and where the static analysis component further identifies a plurality of paths between the first basic block and the second basic block in the control flow graph. … The system where the execution evaluation function uses weighting metrics for the evaluation of basic blocks where weights are defined in relation to the frequency of execution of the basic blocks, and where, a basic block in a loop structure has a higher weight than a basic block which is executed once in a main path);
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Bates to include the one or more processors wherein the one or more processors are further to identify the one or more basic blocks of the control flow graph in the first map based at least on one or more basic block identifiers that uniquely identify individual basic blocks of the control flow graph, as disclosed by Meyer, for the purpose of evaluation function uses weighting metrics for the evaluation of basic blocks where weights are defined in relation to the frequency of execution of the basic blocks. (see paragraph 0077 of Meyer).
Claim 7 is rejected under 35 U.S.C. 103 as being obvious over Bates et al. and Smith et al. as applied to claim 1 in the above and further in view of Liu et al. (US 9286196 B1, hereinafter Liu) and Kielstra et al. (US 8402429 B2, hereinafter Kielstra).
As to claim 7, Bates as modified by Smith does not explicitly disclose the following limitation but,
Liu discloses the one or more processors wherein the first map indicates, based at least on a basic block identifier (ID) (col. 2, ll. 25-28, , performing a topology-based control flow analysis of the basic blocks to associate at least one tag ID with each basic block, wherein a tag ID identifies at least one run-time thread having a given run-time instruction sequence),
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Bates to include the one or more processors wherein the first map indicates, based at least on a basic block identifier (ID), as disclosed by Liu, for the purpose of identifies at least one run-time thread having a given run-time instruction sequence. (see col. 2, ll. 27-28 of Liu).
Kielstra discloses when a declared variable used by the one or more basic blocks has been defined using at least one of the one or more variable definition instructions prior to an entry to the one or more basic blocks (col. 11, ll. 20-35, the compiler 152 uses data flow analysis to create the must-def, the in-sets, and the out-sets for each block in the control flow graph by solving systems of data flow equations. The actual meaning of the dataflow analysis is determined by the specific property that the compiler is determining. The in-sets and out-sets include, for each variable, the set of sub-clique members that may set the variable. As used herein, the in-set or out-set for variable V is denoted as V: {{Sub-Clique1}, {Sub-Clique2}, . . . }, meaning that at the basic block program point where the in-set or out-set is relevant, V is set by an instruction [i.e. definition instructions prior to an entry] in Sub-Clique1 or an instruction in Sub-Clique2, and so forth, if that sub-clique is executed. In each sub-clique, only one member (designated instruction) of the sub-clique actually sets V. The remaining members of the sub-clique set other variables that are also tracked by the compiler in the dataflow in-set/out-set).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Bates to include when a declared variable used by the one or more basic blocks has been defined using at least one of the one or more variable definition instructions prior to an entry to the one or more basic blocks, as disclosed by Kielstra, for the purpose of setting the predicate variable to the predicate value that causes control flow to take the path from the predicate block to the current block. (see abstract of Kielstra).
Claims 11 and 19 are rejected under 35 U.S.C. 103 as being obvious over Smith et al. and Grove et al. (US 5659751 A, hereinafter Grove).
As to claim 11, Smit discloses a system comprising one or more processors to:
generate an output representing a usage of one or more uninitialized variables in the set of instructions based on the correlation (col. 3, ll. 25, a declaration event that indicates an operation on a variable (e.g., an uninitialized variable, an integer variable value of zero); and a failed-assertion event that indicates a determined defect in the source code. Other types of events include a function event that indicates where a function call is initiated in the source code, and includes the input and/or output parameters of the function).
Smith does not explicitly disclose the following limitation but,
Grove discloses generate a first map representative of one or more variables associated with a control flow graph, the control flow graph representing a set of instructions corresponding to source code of a program (col. 2, ll. 33-40, a code optimizer portion which generates a second intermediate code representing the target program generates the target program's live variable set according to the above process so as to map this live variable set to the designated CPU registers of a target computer architecture, wherein said code optimizer inserts, in at least a portion of a control flow graph, dummy blocks representative of a use of a variable in said control flow graph);
correlate one or more variable use instructions from the set of instructions with one or more basic blocks of the control flow graph based on the first map (abstract, … a control flow graph. Basic blocks representing a use of a variable are further added to the control flow graph between the phi functions and definitions of the variables converging at the phi functions. A … . Further, col. 2, ll. 34-39, the target program generates the target program's live variable set according to the above process so as to map this live variable set to the designated CPU registers of a target computer architecture, wherein said code optimizer inserts, in at least a portion of a control flow graph);
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Smith to include generate a first map representative of one or more variables associated with a control flow graph, the control flow graph representing a set of instructions corresponding to source code of a program and correlate one or more variable use instructions from the set of instructions with one or more basic blocks of the control flow graph based on the first map, as disclosed by Grove, for the purpose of more accurately and efficiently identifying live variable sets in a portion of a target computer program. (see abstract of Grove).
As to claim 19, Smith discloses the system wherein the one or more processors are comprised in at least one of:
a system implemented at least partially using cloud computing resources (col. 6, ll. 34-40, The cloud 406 includes and/or is representative of the platform 408 for the networked service components (i.e., the key event manager, source code analysis, and the state machine) that implement embodiments of determining relevant events in source code analysis. The platform abstracts underlying functionality of hardware, such as server devices, and/or software resources of the cloud).
Claim 12 is rejected under 35 U.S.C. 103 as being obvious over Smith et al. and Grove et as application to claim 11 in the above and further in view of Zhang et al. (US 20190102151 A1, hereinafter Zhang).
As to claim 12, Smith as modified by Grove does not explicitly disclose the following limitation but,
Zhang discloses the system wherein the one or more processors are further to:
generate the first map to identify one or more declared variables from the set of instructions (abstract, … the apparatus also includes a PHI handler to replace a PHI instruction contained in the set of instructions with a set of control data flow instructions and a data flow graph generator to map the set of instructions modified by the variable handler and the PHI handler onto a data flow graph without transforming the instructions out of the static single assignment form. Further, par. 0016, … variable instruction identifier 210, an example loop identifier 212 and an example PHI identifier 214. The instruction analyzer 202 examines the SSA formatted instructions stored in the SSA code storage 110 to identify: 1) first information to be used by the variable handler 204) and one or more variable definition instructions from the set of instructions that assign one or more values to the one or more declared variables (par. 0030, the PHI handler 206 is configured to replace all PHI instructions included in the SSA code. PHI instructions are used in SSA formatted code when more than one variable definition reaches a single node. In such circumstances, the value to be assigned to the variable at that node depends on the flow control of the coded instructions dictated by, for example, branching instructions that lead up to the node. An example PHI instruction can take the form, “x=PHI (x3, B3, x4, B4, x5, B5, x6, B6).” In the example PHI instruction, the variable “x3” refers to the value assigned to the variable “x3” at the PHI input block B3, the variable “x4” refers to the value assigned to the variable “x4” at the PHI input block B4, the variable “x5” refers to the value assigned to the variable “x5” at the PHI input block B5 and the variable “x6” refers to the value assigned to the variable “x6” at the PHI input block B6. T).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Smith to include the system wherein the one or more processors are further to: generate the first map to identify one or more declared variables from the set of instructions and one or more variable definition instructions from the set of instructions that assign one or more values to the one or more declared variables, as disclosed by Zhang, for the purpose to convert conventional software instructions to a data flow graph will first convert the software instructions into a form referred to as static single assignment (SSA). However, software in SSA form cannot be directly converted to a data flow graph.. (see par. 0014 of Zhag).
Claim 13 is rejected under 35 U.S.C. 103 as being obvious over Smith et al. and Grove et as application to claim 11 in the above and further in view of Chow et al. (US 6026241 A, hereinafter Chow).
As to claim 13, Smith as modified by Grove does not explicitly disclose the following limitation but,
Chow discloses the system wherein the one or more processors are further to:
correlate one or more variable use instructions based at least on one or more definition-use chains associated with the control flow graph (col. 7, ll. 35-56, In SSA, each definition of a variable is given a unique version, and different versions of the same variable can be regarded as different program variables. Each use of a variable version can only refer to a single reaching definition. By virtue of the versioning, use-def information is built into the representation. Where several definitions of a variable, a.sub.1, a.sub.2, . . . , a.sub.m, reach a confluence point (also called a merging node, or a confluence node) in the control flow graph of the program, a .phi. function assignment statement, a.sub.n .rarw..phi.(a.sub.1, a.sub.2, . . . , a.sub.m), is inserted to merge them into the definition of a new variable version a.sub.n Thus the semantics of single reaching definitions are maintained. This introduction of a new variable version as the result of .phi. factors the set of use-def edges over confluence nodes, reducing the number of use-def edges required to represent the program. In SSA, the use-def chain for each variable can be provided by making each version point to its single definition. One important property of SSA form is that each definition must dominate all its uses in the control flow graph of the program if the uses at .phi. operands are regarded as occurring at the predecessor nodes of their corresponding edges).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Bates to include correlate one or more variable use instructions based at least on one or more definition-use chains associated with the control flow graph, as disclosed by Chow, to represent the program. In SSA, the use-def chain for each variable. (see col. 7, ll. 50-51 of Chow).
Claim 14 is rejected under 35 U.S.C. 103 as being obvious over Smith et al. and Grove et as application to claim 11 in the above and further in view of Mcardle.
As to claim 14, Smith as modified by Grove does not explicitly disclose the following limitation but,
Mcardle discloses the system of claim 11, wherein the set of instructions comprise a static single assignment (SSA) intermediate representation (IR) of the program source code (col. 2, ll. 41-47, executing an application, a processor may access the application binary file from the disk and translate the application binary into intermediate representation. The intermediate representation may be code comprising an intermediate graph structure that allows for flow analysis. Further, col. 7, ll. 37-43, Static Single Assignment (SSA) representation. This property enables the processor to compute reaching definitions using LLVM-based analyses, such as MemorySSA, or other existing implementation. Reaching definitions is a data-flow analysis, which statically determines which definitions may reach a given point in the code).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Smith to include the one or more processors, wherein the set of instructions comprise a static single assignment (SSA) intermediate representation (IR) of the program source code, as disclosed by Mcardle, for the purpose of . (see col. 3, ll. 28-31 of Mcardle).
Claim 15 is rejected under 35 U.S.C. 103 as being obvious over Smith et al. and Grove et as application to claim 11 in the above and further in view of Bates et al. and Simhadri et al.
As to claim 15, Smith as modified by Grove does not disclose the following limitation but,
Bates discloses the system wherein the one or more processors are further to propagate an indication of one or more variable definition instructions to the one or more basic blocks of the control flow graph (par. 0018, FIG. 1 depicts an example method 100 for generating a variable initialization scorecard for computer program source code. The computer program is represented by a control flow graph. In the control flow graph, each node represents a basic block of source code. A basic block of source code is a straight-line code segment without any jumps or jump targets. In a control flow graph, jump targets start a block and jumps end a block. Jumps in the control flow are represented by directed edges between nodes).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Smith to include the system wherein the one or more processors are further to propagate an indication of one or more variable definition instructions to the one or more basic blocks of the control flow graph, as disclosed by Bates, for the purpose to the variable that are defined by the lines of source code. (abstract of Bates).
Simhadri disclosesbased on dominator tree corresponding to a set of basic blocks included in the control flow graph (Figs. 3, 4, the construction of the expression tree for the CFG. Further, col. 6, ll. 64-67, the expression tree corresponding to the else branch (i.e., p is false). This expressions (p, e.sub.t, e.sub.f) captures the contribution of the entire conditional block and hence the block can be logically seen as a single node in the CFG).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Smith to include dominator tree corresponding to a set of basic blocks included in the control flow graph as disclosed by Simhadri, for the purpose of constructing of the expression tree for the CFG and expressions with their corresponding Apply operator types. (see col. 7, ll. 27-29 of Simhadri).
Claim 16 is rejected under 35 U.S.C. 103 as being obvious over Smith et al. and Grove et as application to claim 11 in the above and further in view of Liu et al. and Kielstra et al.
As to claim 16, Smith as modified by Grove does not explicitly disclose the following limitation but,
Liu discloses The system wherein the first map indicates, based at least on a basic block identifier (ID) (col. 2, ll. 25-28, , performing a topology-based control flow analysis of the basic blocks to associate at least one tag ID with each basic block, wherein a tag ID identifies at least one run-time thread having a given run-time instruction sequence),
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Smith to include the one or more processors wherein the first map indicates, based at least on a basic block identifier (ID), as disclosed by Liu, for the purpose of identifies at least one run-time thread having a given run-time instruction sequence. (see col. 2, ll. 27-28 of Liu).
Kielstra discloses when a declared variable used by the one or more basic blocks has been defined using at least one variable definition instruction of one or more variable definition instructions prior to an entry to the one or more basic blocks (col. 11, ll. 20-35, the compiler 152 uses data flow analysis to create the must-def, the in-sets, and the out-sets for each block in the control flow graph by solving systems of data flow equations. The actual meaning of the dataflow analysis is determined by the specific property that the compiler is determining. The in-sets and out-sets include, for each variable, the set of sub-clique members that may set the variable. As used herein, the in-set or out-set for variable V is denoted as V: {{Sub-Clique1}, {Sub-Clique2}, . . . }, meaning that at the basic block program point where the in-set or out-set is relevant, V is set by an instruction [i.e. definition instructions prior to an entry] in Sub-Clique1 or an instruction in Sub-Clique2, and so forth, if that sub-clique is executed. In each sub-clique, only one member (designated instruction) of the sub-clique actually sets V. The remaining members of the sub-clique set other variables that are also tracked by the compiler in the dataflow in-set/out-set).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Bates to include when a declared variable used by the one or more basic blocks has been defined using at least one of the one or more variable definition instructions prior to an entry to the one or more basic blocks, as disclosed by Kielstra, for the purpose of setting the predicate variable to the predicate value that causes control flow to take the path from the predicate block to the current block. (see abstract of Kielstra).
Claim 20 is rejected under 35 U.S.C. 103 as being obvious over Smith et al. and
Meyer et al. (US 20180143813 A1, hereinafter Meyer).
As to claim 20, Smith discloses a system comprising:
processing circuitry to generate an output representing a usage of one or more uninitialized variables in a set of instructions corresponding to a program based at least on one or more maps associated with a control flow graph of the set of instructions (col. 3, ll. 36-26, the key event manager 104 is implemented to log events 110 [i.e. report] that occur during the static code analysis along the executable paths in the source code. In embodiments, the events are logged and used to determine events that are relevant to a user from the analysis. The events 110 can include different event types 112, such as an alias event that indicates at least two variables correspond to a same reference; a branch event that indicates a change of executable paths in the source code 102 (e.g., control flow switch changes), a declaration event that indicates an operation on a variable (e.g., an uninitialized variable)),
Smith does not explicitly disclose the following limitation but,
Meyer discloses to correlate one or more variable use instructions from the set of instructions with one or more basic blocks of the control flow graph based on the one or more maps (par. 00463, the conditional statement in line 08 corresponds to basic block BB8 508. If the condition is true, the read statement for variable “a” in line 09 (corresponding to basic block BB9 509) is executed (YES branch of BB8) and the counter is incremented (line 07 “++i”) corresponding to basic block BB10 510. Otherwise, the counter is directly incremented.. … . Further, par. 0077, … further configured to identify at least one data dependency between a first statement in a first basic block and a second statement in a second basic block where a data flow is indicated from a first processor (p1) to a second processor (p2) of the multi-processor system, and where the static analysis component further identifies a plurality of paths between the first basic block and the second basic block in the control flow graph. … The system where the execution evaluation function uses weighting metrics for the evaluation of basic blocks where weights are defined in relation to the frequency of execution of the basic blocks, and where, a basic block in a loop structure has a higher weight than a basic block which is executed once in a main path);
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Smith to include to correlate one or more variable use instructions from the set of instructions with one or more basic blocks of the control flow graph based on the one or more maps, as disclosed by Meyer, for the purpose of evaluation function uses weighting metrics for the evaluation of basic blocks where weights are defined in relation to the frequency of execution of the basic blocks. (see paragraph 0077 of Meyer).
Allowable Subject Matter
Claims 8-9 and 17-18 are objected to as being dependent upon rejected independent claim 1 and 11, but would be allowable if rewritten in independent form including all of the limitations of independent claims 1, 11 and 20. Claims 9 and 18 are objected based on depended on objected claims.
Conclusion
Prior arts made of record are considered pertinent to applicant's disclosure. See MPEP § 707.05 (C) For Examples:
I. Anushri et al. (EP 4170504 A1) discloses: “ The change-based alarm identification technique comprises identifying, a set of reachable program points of interest (POIs) for the one or more change program points using a control flow graph (CFG) traversal. Further, a set of potentially impacted alarms (PIAs) are determined by evaluating the set of reachable program points of interests (POIs) against the property to be verified using an incrementally computed DFA. The one or more impacted alarms are identified for the set of potentially impacted alarms (PIAs) based on at least one of the (i) OR tag, and (ii) AND tag. Further, inside the modified if statement for potentially impacted alarms (PIAs) are checked based on a true branch condition for the OR tag, and a false branch condition for the AND tag. Furthermore, the potentially impacted alarms (PIAs) are evaluated outside modified if statement for identifying the one or more impacted static analysis alarms by performing the steps of, a transitive data dependency is checked for the set of PIAs controlled by the changed condition for OR tag and tag based on a set of predefined criterions, and (ii) a worklist is created for dependencies on the changed node. The one or more alarms are identified as impacted, if the transitive data dependency node is in false branch of the changed condition for the OR tag, and if the transitive data dependency node is in true branch of the changed condition for the AND tag. Further, determining (i) the transitive data dependency of control dependencies on the changed node and, the transitive control dependencies of data dependency on the changed node, and (ii) a worklist is created for dependencies if any of the dependencies is on the changed node, then the set of PIA's are marked as the one or more impacted static analysis alarms.” (please see [0004]).
II. Nair et al. (US 20090125894 A1) discloses: “A method, system, and computer readable medium for converting a series of computer executable instructions in control flow graph form into an intermediate representation, of a type similar to Static Single Assignment (SSA), used in the compiler arts. The indeterminate representation may facilitate compilation optimizations such as constant propagation, sparse conditional constant propagation, dead code elimination, global value numbering, partial redundancy elimination, strength reduction, and register allocation. The method, system, and computer readable medium are capable of operating on the control flow graph to construct an SSA representation in parallel, thus exploiting recent advances in multi-core processing and massively parallel computing systems. Other embodiments may be employed, and other embodiments are described and claimed.” (please see abstract).
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/Mohammad Kabir/
Examiner, Art Unit 2192
/S. Sough/SPE, Art Unit 2192
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