DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 10 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Coyne (US 2019/0131404).
Regarding claim 1, Coyne disclose A semiconductor device comprising:
a semiconductor layer (layer having channel region 110, Fig. 5, labeled in Fig. 4) having a first surface (top surface of the layer having channel region 110, Fig. 5);
a bottom gate region (bottom gate 104/additional P type region 222, Fig. 5) of a first conductivity type (P type, [0050]) that is formed in the semiconductor layer (layer having channel region 110, Fig. 5);
a top gate region (top gate 112, Fig. 5) of the first conductivity type (p-type, [0042]) that is formed in a surface layer portion of the first surface of the semiconductor layer (a portion of top surface of the layer having channel region 110, Fig. 5) and faces the bottom gate region (facing 104/222, Fig. 5) in a thickness direction of the semiconductor layer (vertical direction, Fig. 5);
a source region (first n type region 118, Fig. 5, [0043]) of a second conductivity (n type, [0043]) type that is formed in a surface layer portion of the first surface of the semiconductor layer (a portion of top surface of the layer having channel region 110, Fig. 5) and is separated from the top gate region (separated from 112, Fig. 5) in a direction along the first surface (lateral direction, Fig. 5);
a drain region (second n type region, Fig. 5, [0043]) of the second conductivity type (n type, [0043]) that is formed in a surface layer portion of the first surface of the semiconductor layer (a portion of top surface of the layer having channel region 110, Fig. 5) and is separated to an opposite side of the source region (opposite side of 118, Fig. 5) from the top gate region (112, Fig. 5) in the direction along the first surface (lateral direction, Fig. 5); and
a channel region (channel region 110, Fig. 5) of the second conductivity type (n type, [0042]), because “in this example the bottom gate 104 is formed of p type material and the channel is formed of n type material” (emphasis added, [0042]) that is formed between the source region and the drain region (between 118 and 120, Fig. 5) in a direction along the first surface (lateral direction, Fig. 5) and is formed between the bottom gate region and the top gate region (between 104/222 and 112, Fig. 5) in the thickness direction of the semiconductor layer (vertical direction, Fig. 5); and
wherein the bottom gate region (104/222, Fig. 5) includes a first bottom gate region at the source region side (left side of 104/222, see attached and annotated Fig. 5 below) and a second bottom gate region at the drain region side (right side of 104/222, see attached and annotated Fig. 5 below), because Applicant did not originally disclose or does not specifically claim what dimensions or boundaries each of the first and second gate regions have and/or whether the first bottom gate region and the second bottom gate region constitute separate gate structures, the Merriam-Webster dictionary defines a word “region” as “an indefinite area of the world or universe”, therefore, an area or a portion of the bottom gate 104/left 222/right 222 by Coyne can be selected for the claimed first and second bottom gate regions; in particular, as shown in the attached and annotated Fig. 5 of Coyne below, the bottom gate 104/left 222/right 222 extends between the source region 118 and the drain region 120, and the left portion of 104/left 222 (i.e., adjacent to the source region 118) corresponds to the claimed first bottom gate region and the right portion of 104/right 222 (i.e., adjacent to the drain region 120) corresponds to the claimed second bottom gate region, respectively, and
an interval in the thickness direction (D2, see Fig. 5 below) between the second bottom gate region (right side of 104/222, Fig. 5) and the top gate region (112, Fig. 5) is greater than an interval in the thickness direction (D1, see Fig. 5 below) between the first bottom gate region (left side of 104/222, Fig. 5) and the top gate region (112, Fig. 5).
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Regarding claim 2, Coyne further discloses for the semiconductor device according to claim 1 that the first bottom gate region (left side of 104/222, Fig. 5) integrally includes a first gate facing portion (portion of 104, Fig. 5) that faces the top gate region (112, Fig. 5) and a first gate lead-out portion (portion of left 222, Fig. 5) that is led out from the first gate facing portion (portion of 104, Fig. 5) to a position below the source region (below 118, Fig. 5) and
the second bottom gate region (right side of 104/222, Fig. 5) integrally includes a second gate facing portion (left portion of right 222, Fig. 5) that faces the top gate region (112, Fig. 5) and a second gate lead-out portion (right portion of right 222, Fig. 5) that is led out from the second gate facing portion (left portion of right 222, Fig. 5) to a position below the drain region (below 120, Fig. 5).
Regarding claim 3, Coyne further discloses for the semiconductor device according to claim 1 that an insulating layer (layer of dielectric 140, Fig. 5) that is formed on the first surface of the semiconductor layer (top surface of the layer having channel layer 110, Fig. 5) and has openings that expose the source region and the drain region (openings for metallic conductors 130 and 132 on 118 and 120, Fig. 5, labeled in Fig. 3).
Regarding claim 10, Coyne further discloses for the semiconductor device according to claim 1 that an insulating layer (layer of dielectric 140, Fig. 5) that is formed on the first surface of the semiconductor layer (top surface of the layer having channel layer 110, Fig. 5) and has a gate opening (opening for gate conductor 134 on 112, Fig. 5, labeled in Fig. 3); and
a gate contact region (gate conductor 134, Fig. 5, labeled in Fig. 3) that is formed in a surface layer portion of the first surface of the semiconductor layer (a portion of top surface of the layer having channel region 110, Fig. 5), is electrically connected to the top gate region (Fig. 5), and is exposed from the gate opening (134, Fig. 5, labeled in Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over by Coyne (US 2019/0131404) in view of Huang et al. (US 10,269,658; hereinafter Huang) The teachings of Coyne are discussed above.
Regarding claim 4, Coyne further disclose that a gate contact region (gate conductor 134, Fig. 5, labeled in Fig. 3) that is formed in a surface layer portion of the first surface of the semiconductor layer (a portion of top surface of the layer having channel region 110, Fig. 5) and is electrically connected in common to the bottom gate region (104/222, Fig. 5) and the top gate region (112, Fig. 5), because “a voltage applied between source 18 and the gates 12 and 14 (often the gates 12 and 14 are electrically connected by a very low resistance path such that they can be regarded as being tied together)…” (emphasis added, [0031], Fig. 1), and the gates 12 and 14 by Coyne corresponds to the claimed top gate region and bottom gate region, respectively.
Coyne does not explicitly disclose that the bottom gate region is formed in an island shape in plan view and the gate contact region in plan view integrally includes a first contact portion that is formed in an annular shape along a peripheral edge portion of the bottom gate region and is electrically connected to the bottom gate region and a second contact portion that is formed across a plurality of locations of the first contact portion such as to segment the bottom gate region and is electrically connected to the top gate region.
However, Huang discloses JFET structure including a top gate 53, a bottom gate 28, and a channel region 42 disposed between the top gate 53 and the bottom gate 28 (Fig. 12). Huang further teaches that in a plan view, the bottom gate 28 is formed in an square-island shape (Fig. 20); P-type pickup regions 36 are disposed in a quadrilateral annular shape (a term “quadrilateral annular shape” is originally disclosed in [0027] of the present application) along a peripheral edge portion of the bottom gate 28 (Figs. 12, 20), and therefore, the P-type pickup region 36 corresponds to the claimed first contact portion, and the P-type pickup region 36 is electrically connected to the bottom gate 28 through the p-well region 32 (Fig. 12); a contact or wire connected to the top gate 53 (Fig. 12), which corresponds to the claimed second contact portion, is disposed across a plurality of locations or regions of the P-type pickup regions 36 (Fig. 20) and the contact or wire is electrically connected to the top gate 53 (Fig. 12). Therefore, Huang teaches the claimed arrangement and one of ordinary skill in the art would have recognized that Huang’s contacts and gate configuration represents a suitable alternative configuration for a JFET having corresponding gate and gate contact arrangement disclosed by Coyne.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Huang’s P-type pickup regions having the quadrilateral annular shape and associated contact arrangement into the JFET structure of Coyne. Such modification would have merely applied Huang’s known gate-contact configuration to Coyne’s JFET structure to provide a known alternative arrangement for electrically contacting the respective gate structures.
Regarding claim 5, Coyne further disclose that the bottom gate region (104/222, Fig. 5) includes the first bottom gate region (left portion of 104/222, see attached and annotated Fig. 5 above) and the second bottom gate region (right portion of 104/222, see attached and annotated Fig. 5 above) that are divided by the second contact portion (134, Fig. 5, labeled in Fig. 3) in plan view, the source region (118, Fig. 5) is formed on the first bottom gate region (left portion of 104/222, Fig. 5), and the drain region (120, Fig. 5) is formed on the second bottom gate region (right portion of 104/222, Fig. 5).
Regarding claim 6, Huang further discloses that the first contact portion (36, Fig. 20) is formed in a quadrilateral annular shape in plan view (Fig. 20) that includes a pair of first rectilinear portions that face each other (left/right or top/bottom portions of 36, Fig. 20) and a pair of second rectilinear portions that face each other (top/bottom or left/right portions of 36, Fig. 20) and the second contact portion (contact or wire connected to 53, Figs. 12, 20) is formed in a rectilinear shape (Fig. 20) that connects the pair of first rectilinear portions (left/right or top/bottom portions of 36, Fig. 20) to each other, because Applicant does not specifically claim how the second contact portion is connected to the pair of first rectilinear portions, i.e., whether they are connected electrically, physically or thermally, as shown in Fig. 12 of Huang, the top gate 53 is electrically connected to the P-type pickup region 36 through the channel region 42 and the p-well region 32.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over by Coyne (US 2019/0131404) in view of Coyne (US 2015/0102391, hereinafter Coyne2) The teachings of Coyne are discussed above.
Regarding claim 11, Coyne does not explicitly disclose that a width of the channel region in the thickness direction of the semiconductor layer is not less than 0.5 μm and not more than 2 μm.
However, Coyne2 discloses a junction field effect transistor structure including a top gate 22, a bottom gate positioned opposite side of the top gate, and channel region between the top gate and the bottom gate (Fig. 6). Coyne2 further teach that “selection of the channel width Wch in the first channel region can be used to move the significant current path away from the areas of high electric field strength, or where the field strength exceeds a maximum permitted E-field value that would initiate impact ionization at the end of the channel region” (emphasis added, [0023]) and “in an embodiment the dimension Wch is greater than about 0.7 microns” (emphasis added, [0058]), therefore, a width of the channel region in the thickness direction by Coyne2 overlaps with the claimed range. Furthermore, Coyne2 recognizes that the width of channel region impacts the current path and electric field strength of JFET device. The width of channel region is therefore a result-effective variable to be optimized by repeated experiments.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, a width of channel region in JFET as Coyne2 has identified the width as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the width not less than 0.5 μm and not more than 2 μm, in order to achieve the desired current path and electric field strength in the channel region, as taught by Coyne2. Furthermore, the applicant has not presented persuasive evidence that the claimed width of channel region is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed width of channel region).
Allowable Subject Matter
Claims 7-9 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior arts cited in this office action do not teach the claim limitations, “a gate intermediate region… has an impurity concentration lower than an impurity concentration of the bottom gate region and an impurity concentration of the gate contact region” recited in claim 7 and claims 8-9 depend on claim 7, and “the interval in the thickness direction between the first bottom gate region and the top gate region is not less than 1/5 and not more than 4/5 of the interval in the thickness direction between the second bottom gate region and the top gate region” recited in claim 12.
Conclusion
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/WOO K LEE/Examiner, Art Unit 2815
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