Prosecution Insights
Last updated: August 18, 2026
Application No. 18/798,016

WIRING BOARD AND SEMICONDUCTOR DEVICE

Non-Final OA §102§112
Filed
Aug 08, 2024
Priority
Aug 10, 2023 — JP 2023-131514
Examiner
CHEN, JACK S J
Art Unit
Tech Center
Assignee
Shinko Electric Industries Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
438 granted / 572 resolved
+16.6% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
45 currently pending
Career history
617
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
31.8%
-8.2% vs TC avg
§102
32.5%
-7.5% vs TC avg
§112
27.3%
-12.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 572 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Re claim 10, line 12, the phrase “the pad” lacks antecedent basis (is it the same as “the metal pad”). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP 5006252 B2. Re claim 1. JP 5006252 B2 discloses a wiring board comprising: an insulating layer 20 (e.g., fig. 14a); and a connection terminal 38 that is formed on a surface of the insulating layer (e.g., fig. 14), wherein the connection terminal includes a pad 18a/26 (e.g., fig. 14A) that is embedded in the insulating layer; and a plated layer 25 (e.g., fig. 14A) that covers an end face of the pad 18a/26 that is exposed on the surface of the insulating layer, the end face of the pad is depressed in a concave surface form to a position lower than the surface of the insulating layer (e.g., fig. 14A), and a surface of the plated layer 25 (e.g., fig. 14A) on a side opposite to a surface making contact with the end face of the pad is depressed in the concave surface form toward the end face, see figs. 1-14 and pages 1-17 for more details. Re claim 2. The wiring board according to claim 1, wherein the end face of the pad has a periphery that is positioned on a same plane as the surface of the insulating layer (e.g., the edges etc., fig. 14A). Re claim 3. The wiring board according to claim 1, wherein the end face of the pad has a periphery that is positioned in a position lower than the surface of the insulating layer (e.g., the center of the recess etc. fig. 14A). Re claim 4. The wiring board according to claim 1, wherein the end face of the pad makes contact with the insulating layer at a periphery (e.g., both sides etc. fig. 14A). Re claim 5. The wiring board according to claim 1, wherein the plated layer is made of nickel 25c (e.g., fig. 14A). Re claim 6. The wiring board according to claim 1, wherein the plated layer 25 is formed astride the insulating layer and the pad in a plane view (e.g, fig. 14). Re claim 7. The wiring board according to claim 1, wherein the insulating layer 20 includes a first insulating layer (e.g., a bottom portion of 20 etc); and a second insulating layer (e.g., a top portion of 20 etc.) that is layered on the first insulating layer, the first insulating layer covers an interconnection layer 30/18b and has an opening that penetrates to the interconnection layer (e.g., figs. 4-10), and the pad is formed in the opening of the first insulating layer (e.g., fig. 14a) and connects to the interconnection layer, protrudes from the opening of the first insulating layer, and is embedded in the second insulating layer at a portion protruding from the opening (e.g., fig. 14a). Re claim 8. The wiring board according to claim 1, wherein the insulating layer covers an interconnection layer 30/18b (e.g., figs. 4-10) and has an opening that penetrates to the interconnection layer, and the pad is formed in the opening of the insulating layer and connects to the interconnection layer (e.g., figs. 4-10 and 14). Re claim 9. The wiring board according to claim 1, wherein the connection terminal further includes a surface processed layer 25a that covers the surface of the plated layer 25c on the side opposite to the surface making contact with the end face of the pad and a side surface of the plated layer (fig. 14). Re claim 10. A semiconductor device comprising: a wiring board 1b (e.g, fig. 14c); and a semiconductor chip 40 (e.g., fig. 14d) that is mounted on the wiring board, the wiring board includes an insulating layer 20 (fig. 14); and a connection terminal 38 (fig. 14) that is formed on a surface of the insulating layer, wherein the connection terminal includes a metal pad 26 (fig. 14a) that is embedded in the insulating layer; and a plated layer 25 that covers an end face of the pad that is exposed on the surface of the insulating layer, the end face of the pad is depressed in a concave surface form to a position lower than the surface of the insulating layer (e.g., fig. 14), a surface of the plated layer on a side opposite to a surface making contact with the end face of the pad is depressed in the concave surface form toward the end face (e.g., fig. 14a), and the semiconductor chip 40 is mounted above the connection terminal and an electrode of the semiconductor chip is joined to the connection terminal 38 with solder 29 that is supplied to the plated layer (e.g., fig. 14), see figs. 1-14 and pages 1-17 for more details. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACK S CHEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Aug 08, 2024
Application Filed
Aug 04, 2026
Non-Final Rejection mailed — §102, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
82%
With Interview (+5.2%)
2y 11m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 572 resolved cases by this examiner. Grant probability derived from career allowance rate.

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