DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/08/2024 and 08/27/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 4 is objected to because of the following informalities:
Claim 4 recites a second magnetic tunnel junction having a first reference layer, first tunneling dielectric and a first free layer. This paragraph appears to be referencing the first magnetic tunnel junction and it is a typographical error that it references the second magnetic tunnel junction. Examination is proceeding with the understanding that the second paragraph of Claim 4 is referring to a first magnetic tunnel junction.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2019/0259809 to Jacob et al (hereinafter Jacob).
Regarding Claim 1, Jacob discloses a magnetoresistive memory device, comprising:
a substrate (Fig. 3; not shown; see [0014]);
a bottom pinned spin-orbit torque (SOT) memory cell (28) located over the substrate, and comprising a first magnetic tunnel junction (22, 24, 26) and a common SOT layer (32, Fig. 2A) located on the first magnetic tunnel junction; and
top pinned SOT memory cell (34) located over the bottom pinned SOT memory cell, and comprising a second magnetic tunnel junction (36, 38, 40) located on the common SOT layer, wherein the common SOT layer is shared between the top pinned SOT memory cell and the bottom pinned SOT memory cell (Fig. 3).
Regarding Claim 2, Jacob discloses the magnetoresistive memory device of Claim 1, further comprising:
a first read line (52) contacting the first magnetic tunnel junction, wherein the first read line located between the substrate and the first magnetic tunnel junction; and
a second read line (54) contacting the second magnetic tunnel junction, wherein the second tunnel junction is located above the first magnetic tunnel junction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5-11 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jacob in view of US PG Pub 2004/0090809 to Tran (hereinafter Tran).
Regarding Claim 3, Jacob discloses the magnetoresistive memory device of Claim 2 but does not disclose a two-terminal selector located in series between the read lines and the magnetic tunnel junctions.
Tran discloses a magnetoresistive memory device having a first two-terminal selector element (110b, Fig. 4) located in series with a first magnetic tunnel junction (108b); and
a second two-terminal selector element (110a) located in series with a second magnetic tunnel junction (108a).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the magnetoresistive memory device of Jacob to have included a two-terminal selector element located in series between the two read lines and their respective magnetic tunnel junctions (MTJ). Jacob discloses selector devices T2/T3 (Fig. 3) that act as selector elements for the MTJ stacks. Utilizing two-terminal selector elements and incorporating them in the stack of materials between the read (52/54) and write lines (32) would have provided obvious benefits such as reducing the footprint of the circuit as demonstrated by Tran. In a combination of the references, two-terminal selector elements would be located between the read lines and MTJ stacks to continue to allow for the independent bit operations utilized by both Jacob [0030] and Tran [0026].
Regarding Claim 5, Jacob discloses a magnetoresistive memory device, comprising:
first read lines (Fig. 3, 52) laterally extending along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction (Fig. 5);
a two-dimensional array of first pillar structures (28, Fig. 3) located on top surfaces of the first read lines, wherein each of the first pillar structures comprises a respective vertical stack including a respective first selector element (see below) and a respective first magnetic tunnel junction (28);
first write lines (32) located on top surfaces of the two-dimensional array of first pillar structures and laterally extending along the second horizontal direction and laterally spaced apart from each other along the first horizontal direction (Fig. 5);
a two-dimensional array of second pillar structures (34) located on top surfaces of the first write lines, wherein each of the second pillar structures comprises a respective vertical stack including a respective second magnetic tunnel junction (34) and a respective second selector element (see below); and
second read lines (54) located on top surfaces of the two-dimensional array of second pillar structures and laterally extending along the first horizontal direction and laterally spaced apart from each other along the second horizontal direction,
wherein each of the first magnetic tunnel junctions comprises a respective first reference layer (Jacob 22), a respective first tunneling barrier layer (Jacob 24), and a respective first free layer (Jacob 26) that is in contact with a respective one of the first write lines.
Jacob does not disclose a selector element located in series between the read lines and the magnetic tunnel junctions.
Tran discloses a magnetoresistive memory device having a first two-terminal selector element (110b, Fig. 4) located in series with a first magnetic tunnel junction (108b); and
a second two-terminal selector element (110a) located in series with a second magnetic tunnel junction (108a).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the magnetoresistive memory device of Jacob to have included a two-terminal selector element located in series between the two read lines and their respective magnetic tunnel junctions (MTJ). Jacob discloses selector devices T2/T3 (Fig. 3) that act as selector elements for the MTJ stacks. Utilizing two-terminal selector elements and incorporating them in the stack of materials between the read (52/54) and write lines (32) would have provided obvious benefits such as reducing the footprint of the circuit as demonstrated by Tran. In a combination of the references, two-terminal selector elements would be located between the read lines and MTJ stacks to continue to allow for the independent bit operations utilized by both Jacob [0030] and Tran [0026].
Regarding Claim 6, the combination of Jacob and Tran makes obvious the magnetoresistive memory device of Claim 5, wherein each of the second magnetic tunnel junctions (Jacob 34, Fig. 3) comprises a respective second reference layer (Jacob 40), a respective second tunneling barrier layer (Jacob 38), and a respective second free layer (Jacob 36) that is in contact with a respective one of the first write lines (Jacob 32).
Regarding Claim 7, the combination of Jacob and Tran makes obvious the magnetoresistive memory device of Claim 5, wherein each of the first pillar structures further comprises a respective synthetic antiferromagnetic structure that is antiferromagnetically coupled to the respective first reference layer, and that is located between the respective first reference layer and the first selector element (Jacob [0018]).
Regarding Claim 8, the combination of Jacob and Tran makes obvious the magnetoresistive memory device of Claim 5, wherein:
each of the first selector elements is in contact with a respective one of the first read lines (T2 would be between read line 52 and MTJ 28 in a combination of the references);
each of the second selector elements is in contact with a respective one of the second read lines (T3 would be between read line 54 and MTJ 34 in a combination of the references);
within each of the first pillar structures, the respective first selector element underlies the respective first magnetic tunnel junction (T2 would be between read line 52 and MTJ 28 in a combination of the references);
within each of the second pillar structures, the respective second selector element overlies the respective second magnetic tunnel junction (T3 would be between read line 54 and MTJ 34 in a combination of the references);
each of the first selector elements comprises a respective first ovonic threshold switch element; and
each of the second selector elements comprises a respective second ovonic threshold switch element.
Regarding Claim 9, the combination of Jacob and Tran makes obvious the magnetoresistive memory device of Claim 5, wherein each of the first write lines (Jacob, 32; Fig. 3) is in contact with top surfaces of first free layers (Jacob 26) of a respective row of first pillar structures within the two-dimensional array of first pillar structures, and is in contact with bottom surfaces of second free layers (Jacob 36) of a respective row of second pillar structures within the two-dimensional array of second pillar structures.
Claim 10, the combination of Jacob and Tran makes obvious the magnetoresistive memory device of Claim 5, wherein:
each of the first pillar structures comprises a respective first straight sidewall that extends from a top surface of a respective one of the first read lines to a bottom surface of a respective one of the first write lines (Jacob Fig. 3; Tran Fig. 11); and
each of the second pillar structures comprises a respective second straight sidewall that extends from a top surface of a respective one of the first write lines to a bottom surface of a respective one of the second read lines (Jacob Fig. 3; Tran Fig. 11).
Regarding Claim 11, the combination of Jacob and Tran makes obvious the magnetoresistive memory device of Claim 5, wherein:
each of the first read lines and the second read lines comprises a first metal selected from Cu or Al at a respective first atomic percentage greater than 50 % (Jacob, [0015]); and
each of the first write lines comprises a second metal having an atomic number in a range from 72 to 79 at a respective second atomic percentage greater than 50 % or a two dimensional material that can induce the spin Hall effect in the first free layers (Jacob [0020]).
Regarding Claim 14, the combination of Jacob and Tran makes obvious the magnetoresistive memory device of Claim 5, further comprising:
a two-dimensional array of third pillar structures (506, Fig. 5) located on top surfaces of the second read lines, wherein each of the third pillar structures comprises a respective vertical stack including a respective third selector element (Jacob 512) and a respective third magnetic tunnel junction (Jacob, Fig. 5 shows multiple pillar structures along additional read lines 514);
second write lines (Jacob 510, Fig. 5) located on top surfaces of the two-dimensional array of second pillar structures and laterally extending along the second horizontal direction and laterally spaced apart from each other along the first horizontal direction;
a two-dimensional array of fourth pillar structures (508 Fig. 5) located on top surfaces of the second write lines, wherein each of the fourth pillar structures comprises a respective vertical stack including a respective fourth magnetic tunnel junction and a respective fourth selector element (Jacob 516); and
third read lines (Jacob 518) located on top surfaces of the two-dimensional array of fourth pillar structures and laterally extending along the first horizontal direction and laterally spaced apart from each other along the second horizontal direction.
Regarding Claim 15, the combination of Jacob and Tran makes obvious a method of operating the magnetoresistive memory device of Claim 5, comprising:
applying an activation voltage greater than a threshold voltage to a selected first read line of the first read lines (Jacob, [0029] & [0032]);
applying a deactivation voltage to unselected first read lines of the first read lines (Jacob, [0029] & [0032]); and
applying a write current to a selected write line of the first write lines to program a selected first magnetic tunnel junction by a spin Hall effect (Jacob, [0029] & [0032]).
Regarding Claim 16, the combination of Jacob and Tran makes obvious the method of Claim 15, further comprising:
applying a read voltage greater than a threshold voltage to the selected first read line (Jacob, [0029] & [0032]); and
applying a read current less than the write current to the selected write current to read the selected magnetic tunnel junction (Jacob, [0029] & [0032]).
Regarding Claim 17, Jacob discloses a method of forming a memory array, comprising:
forming first read lines (Fig. 3, 52) laterally extending along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction over a substrate (Fig. 5);
forming a two-dimensional array of first pillar structures (28) over the first read lines, wherein each of the first pillar structures comprises a respective vertical stack including a respective first selector element (T2, see below) and a respective first magnetic tunnel junction (28), and wherein each of the first magnetic tunnel junctions comprises a respective first reference layer (22), a respective first tunneling barrier layer (24), and a respective first free layer (26);
forming first write lines (32) over the two-dimensional array of first pillar structures, wherein the first write lines laterally extend along the second horizontal direction and are laterally spaced apart from each other along the first horizontal direction (Fig. 5), and wherein each of the first write lines is formed directly on a column of a respective subset of the first free layers (Fig. 3);
forming a two-dimensional array of second pillar structures (34) over the first write lines, wherein each of the second pillar structures comprises a respective vertical stack including a respective second magnetic tunnel junction (34) and a respective second selector element (T3, see below); and
forming second read lines (54) over the two-dimensional array of second pillar structures, wherein the second read lines laterally extend along the first horizontal direction and are laterally spaced apart from each other along the second horizontal direction (Fig. 5).
Jacob does not disclose a selector element located in series between the read lines and the magnetic tunnel junctions.
Tran discloses a magnetoresistive memory device having a first two-terminal selector element (110b, Fig. 4) located in series with a first magnetic tunnel junction (108b); and
a second two-terminal selector element (110a) located in series with a second magnetic tunnel junction (108a).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the magnetoresistive memory device of Jacob to have included a two-terminal selector element located in series between the two read lines and their respective magnetic tunnel junctions (MTJ). Jacob discloses selector devices T2/T3 (Fig. 3) that act as selector elements for the MTJ stacks. Utilizing two-terminal selector elements and incorporating them in the stack of materials between the read (52/54) and write lines (32) would have provided obvious benefits such as reducing the footprint of the circuit as demonstrated by Tran. In a combination of the references, two-terminal selector elements would be located between the read lines and MTJ stacks to continue to allow for the independent bit operations utilized by both Jacob [0030] and Tran [0026].
Regarding Claim 18, the combination of Jacob and Tran makes obvious the method of Claim 17, wherein:
each of the second magnetic tunnel junctions (Jacob, 34) comprises a respective second reference layer (Jacob 36), a respective second tunneling barrier layer (Jacob 38), and a respective second free layer (Jacob 40); and
each of the second free layers is formed directly on a respective one of the first write lines (Jacob Fig. 3).
Regarding Claim 19, the combination of Jacob and Tran makes obvious the method of Claim 17, wherein:
each of the first selector elements is formed directly on a top surface of a respective one of the first read lines (Jacob T2, Fig. 3; in a combination of the references, selector T2 of Jacob would have been formed between the first read line 52 and the MTJ stack 28); and
each of the second read lines is formed directly on top surfaces of a respective subset of the second selector elements (Jacob T2, Fig. 3; in a combination of the references, selector T2 of Jacob would have been formed between the first read line 52 and the MTJ stack 28).
Regarding Claim 20, the combination of Jacob and Tran makes obvious the method of Claim 17, wherein:
each of the first read lines and the second read lines comprises a first metal selected from Cu or Al at a respective first atomic percentage greater than 50 % (Jacob, [0015]); and
each of the first write lines comprises a second metal having an atomic number in a range from 72 to 79 at a respective second atomic percentage greater than 50 % or a two dimensional material that can induce the spin Hall effect in the first free layers (Jacob [0020]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Jacob and Tran as applied to Claim 3 above, and further in view of US PG Pub 2020/0342926 to Katine et al (hereinafter Katine).
Regarding Claim 4, the combination of Jacob and Tran makes obvious the magnetoresistive memory device of Claim 3, wherein:
the common SOT layer (32) comprises a nonmagnetic metal write line (Jacob [0020]) which is electrically connected to a transistor selector element (Jacob, Fig. 3, T1);
the second magnetic tunnel junction comprises a ferromagnetic first reference layer (Jacob, 22; [0018]) located over the first two-terminal selector element (Jacob, Fig. 3, T2 which is between read line 52 and memory cell 28 in a combination of the references), a first tunneling dielectric layer (Jacob 24) located over the first reference layer, and a ferromagnetic first free layer (Jacob 26, Fig. 3) located over the first tunneling dielectric layer and contacting a bottom horizontal surface of the common SOT layer (Jacob 32);
the second magnetic tunnel junction comprises a ferromagnetic second free layer (Jacob 36) located on a top horizontal surface of the common SOT layer (Jacob 32), a second tunneling dielectric layer (Jacob 38) located over the second free layer, and a ferromagnetic second reference layer (Jacob, 40; [0018] & [0021]) located over the second tunneling dielectric layer;
the first two-terminal selector element (Jacob T2; located between read line 52 and MTJ 28 in a combination of the references) comprises a first ovonic threshold switch element (see below); and
the second two-terminal selector element (Jacob T3; located between read line 54 and MTJ 34 in a combination of the references) comprises a second ovonic threshold switch element.
The references do not explicitly disclose the use of an ovonic threshold switch as a selector element.
Katine discloses an ovonic threshold switch (236, Fig. 2B; [0058]) used as a selector element for a magnetic tunnel junction (M.xub.x; Fig. 2B; [0054]). These elements are in series and part of a column of material (Fig. 4A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the two-terminal selector element to comprise an ovonic threshold switch. Ovonic threshold switches would have provided obvious benefits due to the nature of chalcogenide material being able to rapidly block or allow current. Quick switching prevents errors from reading or writing wrong memory cells during operation.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Jacob and Tran as applied to Claim 5 above, and further in view of US PG Pub 2015/0213868 to Wu et al (hereinafter Wu).
Regarding Claim 12, the combination of Jacob and Tran makes obvious the magnetoresistive memory device of Claim 5 but do not disclose the write lines to comprise alternating first and second portions as described by Applicant.
Wu discloses a magnetoresistive memory device, wherein:
each of first write lines (Fig. 4A, A/300/B) comprises alternating first portions (300) and second portions (A/B) which alternate along the second horizontal direction;
the first portions contacts the first free layers (Free M) of the respective first magnetic tunnel junctions (Fig. 4A);
the first portions comprises a material (GSHE, [0040]) that can induce the spin Hall effect in the free layer; and
the second portions (A/B) comprise an electrically conductive material having a higher electrical conductivity than the material of the first portions [0040].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the write lines of Jacob to comprise a first and second portion as defined by Applicant. By including material with higher electrical conductivity between the pillars, signal transmission can be enhanced by reducing a drop in current if utilizing material with lower conductivity.
Regarding Claim 13, the combination of Jacob and Tran makes obvious the magnetoresistive memory device of Claim 5 but do not disclose wherein each of the first pillar structures and the second pillar structures is elongated along the first horizontal direction.
Wu discloses a stacked MTJ structure (Figs. 4A & 4B) wherein the stack is elongated along a direction perpendicular to the write line.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have formed the pillar structures of Jacob to be elongated in the first direction. The first direction is the direction of the read lines in Jacob. Wu discloses in paragraph [0040] that having the easy axis (Fig. 4B) oriented perpendicular to the write line allows for efficient programming of the MTJ stack. The read lines of Jacob are perpendicular to the write line and would therefore be elongated in a first direction with the read lines in a combination of the references.
Conclusion
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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