Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9-14 and 18-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Nakai (U.S. Patent Application 9,754,672).
Claim 1. A method of erasing a memory device including memory cells, comprising: performing a first erase operation on a selected memory cell of the memory cells (S24 Nakai Fig 7 based on Erase at input of S24); performing a first erase verifying operation on the selected memory cell (S25 based on Erase Verify at input of S25); performing a second erase verifying operation on the selected memory cell (S37 Fig 7); and performing a second erase operation on the selected memory cell based on results of the first erase verifying operation and the second erase verifying operation (second erase operation in loop after passing S24 Fig 7 and S37).
Claim 2. The method of claim 1, wherein the first erase verifying operation and the second erase verifying operation are configured to (configured to is functional language) determine a threshold voltage distribution of the selected memory cell after the first erase operation (determine if verify succeeded S26).
Claim 3. The method of claim 2, wherein: a first threshold voltage of the selected memory cell that fails the first erase verifying operation (fail output of S26) is larger than a second threshold voltage of the selected memory cell that passes the first erase verifying operation and fails the second erase verifying operation (output of 29), and the second threshold voltage is larger than a third threshold voltage of the selected memory cell that passes the second erase verifying operation (output of s33. As the signal goes through the loop the threshold voltages get smaller since there are more devices the signal is going through in the loop).
Claim 4. The method of claim 1, wherein the first erase operation is performed based on a first erase voltage (S24 Nakai Fig 7 based on Erase at input of S24) and the second erase operation is performed based on a second erase voltage (S37 Fig 7), and the second erase voltage is larger than the first erase voltage (second erase voltage get additional soft programming making it larger Fig 7).
Claim 9. The method of claim 1, wherein the second erase operation is performed based on the selected memory cell failing one of the first erase verifying operation and the second erase verifying operation (when S36 fails it loops back to S24 through S37 performing a second erase operation on the selected memory cell based on a second erase voltage after the selected memory cell fails the second verifying operation, Nakai Fig 7).
Claim 10. The method of claim 1, wherein the selected memory cell is erased successfully based on the selected memory cell passing the second erase verifying operation (as show in S38 Fig 7).
Claim 11. A memory device, comprising: memory cells including a selected memory cell; and a periphery circuit configured to (configured to is functional language): perform a first erase operation on the selected memory cell (S24 Nakai Fig 7 based on Erase at input of S24); perform a first erase verifying operation on the selected memory cell (S25 based on Erase Verify at input of S25); perform a second erase verifying operation on the selected memory cell (S37 Fig 7); and perform a second erase operation on the selected memory cell based on results of the first erase verifying operation and the second erase verifying operation (second erase operation in loop after passing S24 Fig 7 and S37).
Claim 12. The memory device of claim 11, wherein the first erase verifying operation and the second erase verifying operation are configured to (configured to is functional language) determine a threshold voltage distribution of the selected memory cell after the first erase operation (determine if verify succeeded S26).
Claim 13. The memory device of claim 12, wherein: a first threshold voltage of the selected memory cell that fails the first erase verifying operation (fail output of S26) is larger than a second threshold voltage of the selected memory cell that passes the first erase verifying operation and fails the second erase verifying operation (output of 29), and the second threshold voltage is larger than a third threshold voltage of the selected memory cell that passes the second erase verifying operation (output of s33. As the signal goes through the loop the threshold voltages get smaller since there are more devices the signal is going through in the loop)
Claim 14. The memory device of claim 11, wherein the first erase operation is performed based on a first erase voltage (S24 Nakai Fig 7 based on Erase at input of S24) and the second erase operation is performed based on a second erase voltage (S37 Fig 7), and the second erase voltage is larger than the first erase voltage (second erase voltage get additional soft programming making it larger Fig 7).
Claim 18. The memory device of claim 11, wherein the second erase operation is performed based on the selected memory cell failing one of the first erase verifying operation and the second erase verifying operation (when S36 fails it loops back to S24 through S37 performing a second erase operation on the selected memory cell based on a second erase voltage after the selected memory cell fails the second verifying operation, Nakai Fig 7).
Claim 19. The memory device of claim 11, wherein the selected memory cell is erased successfully based on the selected memory cell passing the second erase verifying operation (as show in S38 Fig 7).
Claim 20. A system, comprising: a memory device including: memory cells including a selected memory cell; and a periphery circuit configured to (configured to is functional language): perform a first erase operation on the selected memory cell (S24 Nakai Fig 7 based on Erase at input of S24); perform a first erase verifying operation on the selected memory cell (S25 based on Erase Verify at input of S25); perform a second erase verifying operation on the selected memory cell (S37 Fig 7); and perform a second erase operation on the selected memory cell based on results of the first erase verifying operation and the second erase verifying operation (second erase operation in loop after passing S24 Fig 7 and S37); and a processor coupled to the memory device and configured to (configured to is functional language) send a command to the memory device (processor must coupled to the memory device for the memory to operate send a command to the memory device).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-8 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nakai (U.S. Patent Application 9,754,672) in view of Ko (U.S. Patent Publication 2020/0202963).
Claim 5. Nakai discloses the method of claim 4 but does not disclose wherein based on the selected memory cell passing the first erase verifying operation and failing the second erase verifying operation, the second erase voltage is equal to the first erase voltage plus a first incremental voltage.
Ko discloses an erase voltage plus a first percent of an incremental voltage (VR2 increment from VR1 Ko Fig 9A) for the purpose of determining whether the memory cells corresponding to the respective target program states of a program operation are completely programmed (Ko [0107]).
Since Nakai and Ko are both from the same field of endeavor (erase verify and NAND strings), the purpose disclosed by Ko would have been recognized in the pertinent art of Nakai.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the incremental erase verify voltage taught by Ko in the circuit taught by Nakai for the purposes of determining whether the memory cells corresponding to the respective target program states of a program operation are completely programmed.
Claim 6. The method of claim 5, wherein, based on the selected memory cell fails the first erase verifying operation, the second erase voltage (VR2 Ko Fig 9A) is equal to the first erase voltage plus a second incremental voltage (as seen in Ko Fig 9A).
Claim 7. The method of claim 6, wherein the first incremental voltage (VR1) is lower than the second incremental voltage (VR2, Ko Fig 9A).
Claim 8. The method of claim 6, wherein the first incremental voltage is 10 percent to 90 percent of the second incremental voltage (as seen in Ko Fig 9A).
Claim 15. Nakai discloses the memory device of claim 14, but does not disclose wherein based on the selected memory cell passing the first erase verifying operation and failing the second erase verifying operation, the second erase voltage is equal to the first erase voltage plus a first incremental voltage.
Ko discloses an erase voltage plus a first percent of an incremental voltage (VR2 increment from VR1 Ko Fig 9A) for the purpose of determining whether the memory cells corresponding to the respective target program states of a program operation are completely programmed (Ko [0107]).
Since Nakai and Ko are both from the same field of endeavor (erase verify and NAND strings), the purpose disclosed by Ko would have been recognized in the pertinent art of Nakai.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the incremental erase verify voltage taught by Ko in the circuit taught by Nakai for the purposes of determining whether the memory cells corresponding to the respective target program states of a program operation are completely programmed.
Claim 16. The memory device of claim 15, wherein, based on the selected memory cell fails the first erase verifying operation (as shown in Fig 7), the second erase voltage is equal to the first erase voltage plus a second incremental voltage (VR2 increment from VR1 Ko Fig 9A).
Claim 17. The memory device of claim 16, wherein the first incremental voltage is lower than the second incremental voltage (VR1 is lower than VR2, Ko Fig 9A).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827