DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim1 is objected to because of the following informalities:
Claim 1, line 5; “a redistribution layer (RDL) on the [[second]] second side of the TFT substrate;”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Liao (US Pub 2014/0264344 A1).
Regarding Claim 1, Liao teaches an electronic device (see Paragraph 0025, “… useful applications in handheld, mobile, or other types of electronic devices, …) including:
a thin film transistor (TFT) substrate (see Paragraph 0039, Fig. 3, “… panels 101' for thin film transistors (TFT's), “) including first side (see Paragraph 0026, Fig. 6, “… a first side 114a...”) and a second side (see Paragraph 0026, Fig. 6, “… a second side 114b ..”);
an array of light emitting diodes (LEDs) (see Paragraph [0025] “FIG. 5 is a top view of LED panels 101' …”) on the first side of the TFT substrate an electrically connected with working circuitry of the TFT substrate (see Paragraph 0026, Fig. 6, “… FIG. 6, which is a cross-sectional view of a treatment method for a glass substrate 102 in accordance with some embodiments. The first film 104 is formed over a first side 114a of the glass substrate 102 that extends in a horizontal direction, and the first film 104 is also formed over a second side 114b of the glass substrate 102 that extends in a horizontal direction, the second side 114b being opposite the first side 114a.”);
a redistribution layer (RDL) on the second side of the TFT substrate (see Paragraph “[0029] In some embodiments, a redistribution layer (RDL) 113a and/or 113b is formed on one or more sides 114a and/or 114b, respectively, of an interposer 101 comprising the glass substrate 102, as shown in FIG. 11. In the embodiment shown in FIG. 11, a first RDL 113a comprising conductive lines or wiring is formed on a first side 114a of the interposer 101 within an insulating material 112, and a second RDL 113b comprising conductive lines or wiring is formed on a second side 114b of the interposer 101…. “); and
a plurality of interconnects extending through the TFT substrate and electrically connected with the RDL (see Paragraph [0029] “In some embodiments, a redistribution layer (RDL) 113a and/or 113b is formed on one or more sides 114a and/or 114b, respectively, of an interposer 101 comprising the glass substrate 102, as shown in FIG. 11. In the embodiment shown in FIG. 11, a first RDL 113a comprising conductive lines or wiring is formed on a first side 114a of the interposer 101 within an insulating material 112, and a second RDL 113b comprising conductive lines or wiring is formed on a second side 114b of the interposer 101. The second side 114b of the interposer 101 is opposite from the first side 114a. ...”).
Regarding Claim 2, Liao teaches the electronic device further comprising a plurality of driver integrated circuit (IC) chips in electrical communication with the plurality of interconnects (see Paragraph [0030] ” … The integrated circuit dies 120, 120', and 120'' include a workpiece comprising silicon or other semiconductor materials which includes active components or circuits (not shown) formed thereon, such as conductive layers and/or semiconductor elements, such as transistors, diodes, resistors, capacitors, inductors, etc. Multiple integrated circuit dies 120 and 120' may be stacked horizontally or vertically (shown in phantom at 120'') over the interposer 101 and packaged together. Contact pads (not shown) on the integrated circuit dies 120 and 120' can be coupled to portions of the RDL 113a ….”).
Regarding Claim 3, Liao teaches the electronic device wherein the plurality of driver IC chips is on the first side of the TFT substrate (see Paragraph [0029] “ … In the embodiment shown in FIG. 11, a first RDL 113a comprising conductive lines or wiring is formed on a first side 114a of the interposer 101 within an insulating material 112, … An insulating material 115 comprising an insulator, polymer, or other materials is formed over the first RDL 113a, between the first RDL 113a and integrated circuit dies 120, 120', and 120'' mounted on the interposer 101.”).
Regarding Claims 4, 6, Liao teaches the electronic device wherein the plurality of driver IC chips is located within a contact ledge area of the TFT substrate (see Paragraph [0023] The glass wafer or panel 100 after the treatment processes comprises a plurality of interposers 101 that can be used to package a plurality of integrated circuit dies, or one or more LCD or LED panels 101'. .. The wafer or panel 100 comprises a portion of an interposer for a three-dimensional integrated circuit (3DIC) in other embodiments. The interposers 101 or LCD or LED panels 101' include the glass substrate 102 and the composite film 104/106 that includes the first film 104 and the second film 106.”).
Regarding Claim 5, Liao teaches the electronic device wherein the plurality of driver IC chips is on the second side of the TFT substrate (see Paragraph [0029] “ … a second RDL 113b comprising conductive lines or wiring is formed on a second side 114b of the interposer 101. … The RDLs 113a and/or 113b may include fan-out regions of wiring, for example. An insulating material 115 comprising an insulator, polymer, or other materials is formed over the first RDL 113a, between the first RDL 113a and integrated circuit dies 120, 120', and 120'' mounted on the interposer 101.”).
Regarding Claim 7, Liao teaches the electronic device wherein the plurality of driver IC chips is located directly behind a display area of the TFT substrate. (see Paragraph [0023] The glass wafer or panel 100 after the treatment processes comprises a plurality of interposers 101 that can be used to package a plurality of integrated circuit dies, or one or more LCD or LED panels 101'. .. The wafer or panel 100 comprises a portion of an interposer for a three-dimensional integrated circuit (3DIC) in other embodiments. The interposers 101 or LCD or LED panels 101' include the glass substrate 102 and the composite film 104/106 that includes the first film 104 and the second film 106.”).
Regarding Claims 8-10, Liao teaches the electronic device further comprising a timing controller chip electrically connected with the RDL; wherein each LED has a maximum dimension of 1 to 100 pm; wherein the array of LEDs is arranged in a curved non-planar display area of the TFT substrate. (see Paragraph [0029] In some embodiments, a redistribution layer (RDL) 113a and/or 113b is formed on one or more sides 114a and/or 114b, respectively, of an interposer 101 comprising the glass substrate 102, as shown in FIG. 11. In the embodiment shown in FIG. 11, a first RDL 113a comprising conductive lines or wiring is formed on a first side 114a of the interposer 101 within an insulating material 112, and a second RDL 113b comprising conductive lines or wiring is formed on a second side 114b of the interposer 101…”).
Regarding Claim 11, Liao teaches the electronic device wherein each LED is an organic light emitting diode (OLED) (see Paragraph (0040] … the composite films 104/106 are implementable in end products such as LCD panels, 3D light emitting diode (LED) smart TV's, organic LED's (OLED's), smart phone displays, and other applications, as examples.”).
Regarding Claims 12, 13, Liao teaches the electronic device wherein the electronic device is incorporated into a wearable electronic device; one or more IC chips on the RDL and directly behind a display area of the TFT substrate. (See Paragraph [0029] “The RDLs 113a and/or 113b may include fan-out regions of wiring, for example. An insulating material 115 comprising an insulator, polymer, or other materials is formed over the first RDL 113a, between the first RDL 113a and integrated circuit dies 120, 120', and 120'' mounted on the interposer 101. .…”).
Regarding Claim 14, Liao teaches the electronic device wherein the IC chips are selected from the group consisting of a power management IC, a processor, a memory, and a communications IC (see Paragraph [0040] The glass substrates 102 including the composite films 104/106 can be implemented in 3DIC packaging for heterogeneous system integration of a 20 nm logic processer, a 65 nm RF device, and a 45 nm memory device within a single CoWoS package in some applications, for example. The glass substrates 102 including the composite films 104/106 are implementable in high-frequency mobile communication devices (e.g., as high or higher than 60 GHz) such as i-phones, i-pads, ultrabooks, smart phones, smart TVs, and cloud computing devices.”).
Conclusion
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
It is noted that any citation to specific pages, columns, figures, or lines in the prior art references any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331-33, 216 USPQ 1038-39 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)).
Examiner’s Note
Examiner has cited particular paragraphs/columns and line numbers or figures in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicant’s definition which is not specifically set forth in the claims.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIJAY SHANKAR whose telephone number is (571)272-7682. The examiner can normally be reached M-F 9 am- 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VIJAY SHANKAR
Primary Examiner
Art Unit 2624
/VIJAY SHANKAR/Primary Examiner, Art Unit 2624