DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in REPUBLIC OF KOREA on 08/14/2023. It is noted, however, that applicant has not filed a certified copy of the KR10-2023-0106416 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-10, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. Patent No. 10,770,499) in view of Yanagita et al. (U.S. Patent No. 9,923,010).
Regarding to claim 1, Kim teaches an image sensing device comprising:
a plurality of unit pixels configured to generate electrical signals based on incident light and arranged in a row direction or a column direction of a pixel array (Fig. 9, column 6, lines 46-47),
wherein the plurality of unit pixels includes a first unit pixel (Fig. 9, the left unit pixel), wherein the first unit pixel includes:
a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in a 2 x 2 matrix (Fig. 9, first sub-pixel including PD1L, a second sub-pixel including PD1R, a third sub-pixel including PD2L and a fourth sub-pixel including PD2R);
an isolation structure (Fig. 9, element 32) including a first portion and a second portion, the first portion formed to surround the first unit pixel (Fig. 9, please see the attached figure), the
second portion disposed between adjacent sub-pixels among the first sub-pixel to the fourth sub-pixel (Fig. 9, please see the attached figure);
a first junction region formed to surround a first transistor region and disposed across the first sub-pixel and the second sub-pixel along a first side of the first unit pixel (Fig. 9, please see the attached figure, junction region including n+ dopant area); and
a second junction region formed to surround a second transistor region and disposed across the third sub-pixel and the fourth sub-pixel along a second side parallel to the first side (Fig. 9, please see the attached figure, junction region including n+ dopant area).
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Kim is silent about a size ratio of the unit pixel.
Yanagita generally discloses a length of the first side is close to a length of a third side of the first unit pixel perpendicular to the first side (Fig. 3). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in view of Yanagita to configure a length of the first side to be equal to a length of a third side of the first unit pixel perpendicular to the first side, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 8, Kim teaches the first transistor region includes a drive transistor (Fig. 9, column 8, lines 37-38) and a selection transistor (Fig. 9, column 8, lines 44-45); and the second transistor region includes a gain conversion transistor (Fig. 9, column 8, lines 37-38) and a reset transistor (Fig. 9, column 8, line 40).
Regarding to claim 9, Yanagita teaches each of the first to fourth sub-pixels is formed in a square shape (Fig. 3).
Regarding to claim 10, Kim teaches the plurality of unit pixels includes a second unit pixel in contact with the first unit pixel (Fig. 9, the left unit pixel), wherein the second unit pixel includes:
a third junction region formed to surround a third transistor region and disposed across a fifth sub-pixel (Fig. 9, sub-pixel including PD4L) and a sixth sub-pixel (Fig. 9, sub-pixel including PD4R) along a fifth side of the second unit pixel (Fig. 9, similar to first unit pixel); and
a fourth junction region formed to surround a fourth transistor region and disposed across a seventh sub-pixel (Fig. 9, sub-pixel including PD3L) and an eighth sub-pixel (Fig. 9, sub-pixel including PD3R) along a sixth side parallel to the fifth side (Fig. 9, similar to first unit pixel),
wherein the fifth side is in contact with a fourth side of the first unit pixel extending in a direction perpendicular to the first side (Fig. 9, similar to first unit pixel).
Regarding to claim 13, Kim teaches the first transistor region includes a plurality of pixel transistors connected in parallel to each other (Fig. 9).
Regarding to claim 14, Kim teaches the pixel transistors include at least one of a drive transistor, a selection transistor, a reset transistor, or a gain conversion transistor (column 8, lines 40-44).
Regarding to claim 15, Kim teaches the first unit pixel further includes a ground region disposed at a center of the first unit pixel and configured to receive a ground voltage as an input (Fig. 10, Fig. 8).
Regarding to claim 16, Kim teaches the second transistor region includes a capacitive element (column 6, lines 8-10).
Claims 2-7, 11-12, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. Patent No. 10,770,499) and Yanagita et al. (U.S. Patent No. 9,923,010), as applied to claim 1 above, further in view of Pyo et al. (U.S. Patent No. 10,886,318).
Regarding to claim 2, Kim as modified does not disclose each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes two photoelectric conversion elements that generate photocharge in response to incident light and disposed adjacent to each other. Pyo discloses each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes two photoelectric conversion elements that generate photocharge in response to incident light and disposed adjacent to each other (Fig. 5A. Fig. 6A, Fig. 7A, elements 110a/110b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in view of Pyo to include in each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel two photoelectric conversion elements that generate photocharge in response to incident light and disposed adjacent to each other in order to increase resolution of sensitivity.
Regarding to claim 3, Pyo discloses the two photoelectric conversion elements are arranged adjacent to each other in the row direction or the column direction of the pixel array (Fig. 5A).
Regarding to claim 4, Pyo discloses each of the first to fourth sub-pixels includes transfer transistors that respectively overlap the two photoelectric conversion elements (Fig. 7A).
Regarding to claim 5, Kim teaches each of the photoelectric conversion elements includes a deep-doped region where impurities are doped to a first depth from a surface of the first unit pixel and a shallow-doped region where impurities are doped to a second depth from the surface of the first unit pixel, wherein the second depth is closer to the surface of the first unit pixel than the first depth (Fig. 2, n region 42 and n- region 44).
Regarding to claim 6, Kim teaches the first unit pixel includes: a first floating diffusion region disposed between the first subpixel and the third sub-pixel (Fig. 9, left half portion of FD1 between the first subpixel and the third sub-pixel); and a second floating diffusion region disposed between the second sub-pixel and the fourth sub-pixel (Fig. 9, right half portion of FD1 between the second sub-pixel and the fourth sub-pixel).
Regarding to claim 7, Kim teaches the first floating diffusion region and the second floating diffusion region are arranged in a direction in which the first side extends (Fig. 7).
Regarding to claim 11, Kim as modified discloses the plurality of unit pixels includes a second unit pixel in contact with the first unit pixel (Fig. 9, the left unit pixel), wherein the second unit pixel includes:
a fifth sub-pixel (Fig. 9, sub-pixel including PD4L), a sixth sub-pixel (Fig. 9, sub-pixel including PD4R), a seventh sub-pixel (Fig. 9, sub-pixel including PD3L), and an eighth sub-pixel (Fig. 9, sub-pixel including PD3R) arranged in a 2x2 matrix (Fig. 9), wherein:
each of the fifth sub-pixel, the sixth sub-pixel, the seventh subpixel, and the eighth sub-pixel includes two photoelectric conversion elements (Kim as modified in view of Yanagita results this); and
the photoelectric conversion elements included in each of the fifth sub-pixel, the sixth sub-pixel, the seventh sub-pixel, and the eighth sub-pixel are arranged to be adjacent to each other in a direction perpendicular to a direction in which photoelectric conversion elements included in each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged (Fig. 9).
Regarding to claim 12, Kim teaches the second unit pixel further includes:
a third floating diffusion region disposed between the fifth subpixel and the seventh sub-pixel (Fig. 9, left half portion of FD3 between the fifth subpixel and the seventh sub-pixel); and
a fourth floating diffusion region disposed between the sixth subpixel and the eighth sub-pixel (Fig. 9, right half portion of FD2 between the sixth subpixel and the eighth sub-pixel),
wherein the third floating diffusion region and the fourth floating diffusion region are arranged in a direction in which the photoelectric conversion elements included in each of the fifth sub-pixel, the sixth sub-pixel, the seventh sub-pixel, and the eighth sub-pixel are arranged (Fig. 9).
Regarding to claim 17, Kim teaches the isolation structure is formed in a trench structure extending from one surface of a semiconductor substrate toward another surface opposite to the one surface of the semiconductor substrate, and wherein the semiconductor substrate is which the photoelectric conversion elements are arranged (column 10, lines 1-3).
Regarding to claim 18, Kim teaches the first junction region or the second junction region is an impurity region extending from the other surface of the semiconductor substrate toward the one surface of the semiconductor substrate (column 9, lines 51-55).
Regarding to claim 19, Kim teaches the first junction region or the second junction region is formed to at least partially overlap the isolation structure (Fig. 9).
Regarding to claim 20, Kim teaches a width of the first junction region or a width of the second junction region is smaller than a width of the isolation structure surrounding the first unit pixel (Fig. 9).
Pertinent Art
For the benefits of the Applicant, US-20230411418-A1, US-11804510-B2, US-11961856-B2, US-9270915-B2, US-7244920-B2, US-8471312-B2, US-8922686-B2, and US-12364046-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose “a second junction region formed to surround a second transistor region and disposed across the third sub-pixel and the fourth sub-pixel along a second side parallel to the first side, wherein a length of the first side is equal to a length of a third side of the first unit pixel perpendicular to the first side.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
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/VU A VU/Primary Examiner, Art Unit 2897
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