Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on 9/11/2023. It is noted, however, that applicant has not filed a certified copy of the Japanese application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/8/2024 was filed before the mailing date of the Non-final rejection on 9/19/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The formal drawings filed on 8/8/2024 have been approved by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “HEAT DISSIPATION MEMBER ATTACHED TO SEMICONDUCTOR DEVICE ”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Hitachi (JP 1-270336).
With respect to Claim 1, Hitachi teaches a semiconductor element (i.e. SOP IC) and a sealing resin 66 that has a first main surface, a second main surface opposed to the first main surface, a first side surface connecting the first main surface and the second main surface. A second side surface connecting the first main surface and the second main surface and opposed to the first side surface. A third side surface connecting the first main surface and the second main surface and located between the first side surface and the second side surface. A fourth side surface connecting the first main surface and the second main surface and opposed to the third side surface, and seals the semiconductor element. A plurality of terminals 7, 45, 47 electrically connected to the semiconductor element, protruding from the first side surface and the second side surface of the sealing resin 66. Extending to a height position of the second main surface, wherein a heat dissipation member 18, 58 is disposed on the first main surface of the sealing resin 66. A control board 81 to which the plurality of terminals 45, 47 are electrically connected is disposed on the second main surface of the sealing resin. The semiconductor device further comprises a plurality of portions 60 to be joined that protrude from the third side surface and the fourth side surface of the sealing resin, are joined to the control board, and are not electrically (i.e. use to support the semiconductor package) connected to the semiconductor element (see specification, page 412; Figs. 1a, 2-14, 17, 20, and 21).
With respect to Claim 2, Hitachi teaches the plurality of terminals 7, 45, 47 extend in directions away from the sealing resin at the height position of the second main surface of the sealing resin (see Figs. 11, 12, 14, 17, 20, and 21).
With respect to Claim 4, Hitachi teaches the plurality of portions 60 to be joined extend to the height position of the second main surface of the sealing resin 65 (see Figs. 11, 12, 14, and 19-21).
With respect to Claim 7, Hitachi teaches materials of the plurality of terminals 7, 45, 47 and the plurality of portions to be joined are same, but the plurality of portions 60 to be joined electrically floating (see 13, 14, and 17).
With respect to Claim 8, Hitachi teaches portions of the plurality of terminals 7, 45, 47 protruding from the sealing resin 66 are located at a height position between the
first main surface and the second main surface of the sealing resin (see Figs. 1, 10, 20, and 21).
With respect to Claim 8, Hitachi teaches on the control board 81 and the plurality of portions 60 to be joined are joined to the control board simultaneously with the plurality of terminals by reflow soldering (see Figs. 20 and 21).
Allowable Subject Matter
Claims 3, 5, 6, and 10-12 are objected to as being dependent upon a rejected
base claim, but would be allowable if rewritten in independent form including all of the
limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record teaches or suggest the combination of
a hole for screwing is provided in each of the plurality of portions to be joined. The plurality of portions to be joined are screwed to the control board to join the
portions to be joined and the control board to each other in claim 3.
A pin to be inserted into a hole provided in the control board is provided at a distal end portion of each of the plurality of portions to be joined in claim 5.
Conclusion
9. Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/September 19, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
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