Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-10, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Takado (20170104093), in view of Otake (20200176595).
Regarding claim 1, Takado teaches a nitride semiconductor device, comprising:
an electron travelling layer (fig. 18: 4), made of a nitride semiconductor (par. 67, 68 and 89);
an electron supply layer (fig. 18: 32 + 33), formed on the electron travelling layer and made of a nitride semiconductor having a band gap larger than a band gap of the electron travelling layer (par. 89 teaches materials used for electron supply layer has a larger bandgap);
a gate electrode (fig. 18: 12);
a passivation layer (fig. 18: 6 + 7), covering the electron supply layer and the gate electrode, and having a source opening and a drain opening separated from the source opening (please see fig. 18 which shows these openings in 6),
a source electrode (fig. 18: 13), in contact with the electron supply layer through the source opening (please see fig. 18); and
a drain electrode (fig. 18: 14), in contact with the electron supply layer through the drain opening (please see fig. 18),
wherein the electron travelling layer includes:
a first portion (fig. 18, portion labeled Ec > Ef), located under the gate electrode; and
a second portion, located between the gate electrode and the source opening, and located between the gate electrode and the drain opening in a plan view (fig. 18, please see the portions labeled Ec < Ef),
the electron supply layer includes:
a first electron supply layer, formed on the first portion and located below the gate electrode (fig. 18: 33); and
a second electron supply layer, formed on the second portion and connected to the first electron supply layer (fig. 18: 32).
Takada fail to teach:
a gate layer under the gate electrode, formed on a portion of the electron supply layer and made of a nitride semiconductor including acceptor-type impurities wherein the gate layer is interposed between the source opening and the drain opening
Otake teaches a HEMT, similar to the HEMT taught in Takada, wherein a gate layer (fig. 1: 21), doped with acceptor impurities (par. 57), is placed between the gate electrode (fig. 1: 23) and the electron supply layer (fig. 1: 5), as well as between the S/D electrodes. It is common knowledge in the art that in HEMTs, gate layers under gate electrodes controls the flow of current between the source and drain by modulating the width of the 2DEG channel through electrostatic control. The use of the gate layer in Takada would impart this benefit to the device taught in Takada. Further, these prior art are related to similar fields of endeavor i.e. HEMT devices.
For at least these reasons, it would have been obvious to a PHOSITA, at the time of filing, to utilize aforementioned teachings of the prior art(s) in the primary prior art(s) due to aforementioned reason(s).
Regarding claim 7, Takado, in view of Otake, teaches a nitride semiconductor device of claim 1, wherein an upper surface of the second portion of the electron travelling layer is coplanar with an upper surface of the first portion of the electron travelling layer (please see Takado, fig. 11).
Regarding claim 8, Takado, in view of Otake, teaches a nitride semiconductor device of claim 1, wherein a thickness of the second electron supply layer is same as a thickness of the first electron supply layer (Takada, par. 68).
Regarding claim 9, Takado, in view of Otake, teaches a nitride semiconductor device of claim 1, wherein the passivation layer includes: a first passivation layer (Takada, 6), covering the second electron supply layer; and a second passivation layer (Takada, 7), covering the first passivation layer and the gate electrode.
Regarding claim 10, Takado, in view of Otake, teaches a nitride semiconductor device of claim 1, wherein the electron travelling layer is GaN layer (Takada, par. 89), the electron supply layer is AlGaN layer (Takada , par. 89), and the gate layer is GaN layer including acceptor-type impurities (Otake, par. 57).
Regarding claim 16, Takado, in view of Otake, teaches a nitride semiconductor device of claim 7, wherein the electron travelling layer is GaN layer (Takada, par. 89), the electron supply layer is AlGaN layer (Takada , par. 89), and the gate layer is GaN layer including acceptor-type impurities (Otake, par. 57).
Regarding claim 17, Takado, in view of Otake, teaches a nitride semiconductor device of claim 8, wherein the electron travelling layer is GaN layer (Takada, par. 89), the electron supply layer is AlGaN layer (Takada , par. 89), and the gate layer is GaN layer including acceptor-type impurities (Otake, par. 57).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 11 is objected to based on its dependency on claim 2.
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4-6 and 12 are objected to based on their dependence on claim 3.
Claims 13-15 are objected to based on their dependence on claim 4-6.
Claims 18-20 allowed.
The following is an examiner’s statement of reasons for allowance: prior art fails to teach the temporal ordering of steps outlined in claim 18, such as forming a gate layer made of a nitride semiconductor including acceptor-type impurities on the initially formed electron supply layer; removing a portion of the initially formed electron supply layer by etching to expose the electron travelling layer while leaving a portion under the gate layer, thereby forming a first electron supply layer which is a remaining portion of the initially formed electron supply layer; forming a re-formed electron supply layer connected to the first electron supply layer on the electron travelling layer exposed by etching; forming a passivation layer on the re-formed electron supply layer; forming a gate electrode over the gate layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CALEB E HENRY/Primary Examiner, Art Unit 2818
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