Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 9th, 2024 was filed before the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s)
Claims 1 - 3, 5, 6, 8-13, and 15 - 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20230029098 A1; hereinafter Kim) view of Nakagawa et al. (US 20120018726 A1; hereinafter Nakagawa).
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Annotated Fig. 4 – Kim
Regarding claim 1, Kim teaches a semiconductor package (Fig. 4: semiconductor package 40; [0064]), comprising:
a first semiconductor chip having a chip mounting region on a central portion of an upper surface of the first semiconductor chip (see annotated Fig. 4: semiconductor chip 100, and mounting region is a width of the connecting structures comprising second lower bump pad 230, second connection terminal 240, and first bump pad 160; [0068]) and a test region surrounding the chip mounting region;
a plurality of first measurement structures on the test region and sequentially arranged in a direction perpendicular to an edge of the chip mounting region to be spaced apart from the edge of the chip mounting region;
a second semiconductor chip (Fig. 4: second semiconductor chip 200; [0069]) mounted on the chip mounting region of the first semiconductor chip via a plurality of conductive bumps (Fig. 4: second connection terminal 240 is equivalent to bump structure BS which has a ball structure; [0033] and [0069]);
an adhesive layer filling a gap between the first semiconductor chip and the second semiconductor chip, and the adhesive layer including a central portion on the chip mounting region and at least one overflow portion protruding from the central portion to the test region (See annotated Fig. 4: non-conductive film NCF covers the entire semiconductor chip 100, including the mounting and edge regions, wherein the overflow portion covers the edge region and the side portion of the semiconductor chips 100 and 200, the edge region being where the testing region would reside) to contact at least one of the plurality of first measurement structures; and
a molding member on the upper surface of the first semiconductor chip to cover side surfaces of the second semiconductor chip (Fig. 4: molding member 600 surrounding semiconductor chips 100 and 200; [0079]).
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Annotated zoomed in Fig. 2 – Nakagawa
However, Nakagawa teaches the following limitations not explicitly taught by Kim:
a test region surrounding the chip mounting region (see annotated Fig. 2: test region is surrounding the central area);
a plurality of first measurement structures on the test region and sequentially arranged in a direction perpendicular to an edge of the chip mounting region to be spaced apart from the edge of the chip mounting region (see annotated Fig. 2 and Fig. 4A-C: inter-chip connects 6 connected to inter test-pad interconnects 5 are disposed spaced apart at different distances going out from the central region in a top-down view);
Nakagawa also teaches in paragraph 3, that in a general manufacturing process for a semiconductor device, functionality tests are conducted in order to test the functions of a semiconductor chip formed on the semiconductor wafer before moving to a subsequent assembling steps.
It would have been to one of ordinary skill in the art to combine the semiconductor package of Kim with the measurement structures in an edge/test area of Nakagawa in order to test the functionality of the semiconductor chip before mounting the second chip, and to also cover the measurement structures with the adhesive NCF, either directly or indirectly, in order to electrically isolate the measurement structures that are no longer in use after manufacturing.
Regarding claim 2, Kim does not explicitly teach the semiconductor package of claim 1, wherein each of the plurality of first measurement structures extends in a second direction perpendicular to a first direction in which the edge of the chip mounting region extends.
However, Nakagawa teaches wherein each of the plurality of first measurement structures extends in a second direction perpendicular to a first direction in which the edge of the chip mounting region extends (see annotated Fig. 2 and Fig. 4A-C: first measurement structures are inter-chip connects 6 connected to inter test-pad interconnects 5 that run along the edge of the central region in a direction parallel to the mounting region, and disposed spaced apart at different distances going out from the central region in a top-down view).
Regarding claim 3, Kim teaches wherein the semiconductor package of claim 1, wherein the adhesive layer includes a non-conductive film (NCF) (Fig. 4: adhesive is formed of a non-conductive film NCF; [0034]).
Regarding claim 5, Kim does not explicitly teach the semiconductor package of claim 1, further comprising: a plurality of second measurement structures extending from the chip mounting region to the test region.
However, Nakagawa teaches further comprising: a plurality of second measurement structures extending from the chip mounting region to the test region (See zoomed in annotated Fig. 2: test pads 4 disposed at the end of the edge of the chip mounting region and connected to inter-test pad interconnects 5 which extend inwards towards the central region, perpendicular to the edge).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the semiconductor package of Kim with the measurement structures of Nakagawa in order to have a peripheral test structure that connects further into the chip from the edge, so that the chip functionality can be measured without probing the chip directly.
Regarding claim 6, Kim does not explicitly teach the semiconductor package of claim 5, wherein the central portion of the adhesive layer is in contact with at least one of the plurality of second measurement structures.
However, Kim teaches in Fig. 4 (see annotated Fig. 4), that the adhesive layer NCF surrounds the entire semiconductor chip 100, including the central mounting region and the peripheral edge region. Kim also teaches in paragraph 34, that the adhesive layer may be formed of a non-conductive film (NCF).
Nakagawa teaches in Fig. 2 (see annotated Fig. 2), that the second measurement structures, test pads 4 with the inter-test pad interconnects 5, are in the peripheral edge region.
It would have been obvious to one of ordinary skill in the art to combine the adhesive non-conductive film connection of Kim with the measurement structures of Nakagawa in order to electrically isolate the measurement structures after they are no longer in use, either by directly or indirectly, contacting the measurement structures disposed on the semiconductor chip.
Regarding claim 8, Kim teaches the semiconductor package of claim 1, wherein the first semiconductor chip includes:
a first substrate (Fig. 4: first substrate 101; [0068]),
a plurality of through electrodes penetrating the first substrate (Fig. 4: first through-electrode 150; [0068]),
a first wiring layer on a first surface of the first substrate (Fig. 4: first semiconductor device layer 110 disposed on an underside of the first substrate 101 and containing first interconnection layer 120; [0068]),
the first wiring layer having a plurality of first redistribution pads (Fig. 4: first connection pad 130 disposed on the underside and connected to the interconnection layer 120; [0024]),
a plurality of first bonding pads respectively disposed on the plurality of first redistribution pads (Fig. 4: upper surface pad 530 connected to the first connection pads 130 through first connection terminals 140).
Regarding claim 9, Kim does not explicitly teach the semiconductor package of claim 8, wherein the plurality of first measurement structures are electrically connected to the plurality of first bonding pads via at least one of the plurality of through electrodes of the first semiconductor chip and via the first wiring layer.
However, Nakagawa teaches wherein the plurality of first measurement structures are electrically connected to the plurality of first bonding pads via at least one of the plurality of through electrodes of the first semiconductor chip and via the first wiring layer (See annotated Fig. 2 and Fig. 3A-C: the interconnection layers are connected through vias to input/output pads 7).
It would have been obvious to one of ordinary skill in the art to combine the semiconductor package of Kim with the through vias of Nakagawa in order to connect the test region with the pads for electrical functionality testing of the semiconductor chip.
Regarding claim 10, Kim teaches the semiconductor package of claim 8, wherein
the first semiconductor chip has a second surface opposite to the first surface (Fig. 4: the upper surface of the semiconductor chip 100 with first bump pads 160; [0068] – [0070]), wherein
the first semiconductor chip has a plurality of second bonding pads on the second surface (Fig. 4: first bump pads 160 disposed on the upper surface of semiconductor chip 100; [0068] – [0070]), and
the plurality of conductive bumps are respectively disposed on the plurality of second bonding pads (Fig. 4: second connection terminal 240 disposed on bump pads 160 and electrically connect first semiconductor chip 100 and the second semiconductor chip 200; [0068] – [0070]).
Regarding claim 11, Kim teaches A semiconductor package, comprising:
a first semiconductor chip having a chip mounting region on a central portion of an upper surface of the first semiconductor chip (Fig. 4: The mounting region is a width of the connecting structures comprising second lower bump pad 230, second connection terminal 240, and first bump pad 160) and a test region surrounding the chip mounting region;
a plurality of first measurement structures on the test region and sequentially arranged to be spaced apart from an edge of the chip mounting region;
a plurality of second measurement structures extending from the chip mounting region to the test region;
a second semiconductor chip (Fig. 4: second semiconductor chip 200; [0069]) mounted on the chip mounting region of the first semiconductor chip via a plurality of conductive bumps (Fig. 4: second connection terminal 240 is equivalent to bump structure BS which has a ball structure; [0033] and [0069]);
an adhesive layer filling a gap between the first semiconductor chip and the second semiconductor chip, and the adhesive layer including a central portion on the chip mounting region and at least one overflow portion protruding from the central portion to the test region (See annotated Fig. 4: non-conductive film NCF covers the entire semiconductor chip 100, including the mounting and edge regions, however is not explicit to the measurement structures overflow portion surrounds the sides of the semiconductor chips, which includes the edge region where testing would be) to contact at least one of the plurality of first measurement structures; and
a molding member on the upper surface of the first semiconductor chip to cover side surfaces of the second semiconductor chip (Fig. 4: molding member 600 surrounding semiconductor chips 100 and 200; [0079]).
However, Nakagawa teaches the following limitations not explicitly taught by Kim:
a test region surrounding the chip mounting region (see annotated Fig. 2: test region is surrounding the central area);
a plurality of first measurement structures on the test region and sequentially arranged in a direction perpendicular to an edge of the chip mounting region to be spaced apart from the edge of the chip mounting region (see annotated Fig. 2 and Fig. 4A-C: inter-chip connects 6 connected to inter test-pad interconnects 5 are disposed spaced apart at different distances going out from the central region in a top-down view);
a plurality of second measurement structures extending from the chip mounting region to the test region (See zoomed in annotated Fig. 2: test pads 4 disposed at the end of the edge of the chip mounting region and connected to inter-test pad interconnects 5 which extend inwards towards the central region, perpendicular to the edge);
Nakagawa also teaches in paragraph 3, that in a general manufacturing process for a semiconductor device, functionality tests are conducted in order to test the functions of a semiconductor chip formed on the semiconductor wafer before moving to a subsequent assembling steps.
It would have been to one of ordinary skill in the art to combine the semiconductor package of Kim with the measurement structures in an edge/test area of Nakagawa in order to test the functionality of the semiconductor chip before mounting the second chip, and to also cover the measurement structures with the adhesive NCF, either directly or indirectly, in order to electrically isolate the measurement structures that are no longer in use after manufacturing.
Regarding claim 12, Kim does not explicitly teach the semiconductor package of claim 11, wherein each of the plurality of first measurement structures extends in a second direction perpendicular to a first direction in which the edge of the chip mounting region extends.
However, Nakagawa teaches wherein each of the plurality of first measurement structures extends in a second direction perpendicular to a first direction in which the edge of the chip mounting region extends (see annotated Fig. 2 and Fig. 4A-C: first measurement structures are inter-chip connects 6 connected to inter test-pad interconnects 5 that run along the edge of the central region in a direction parallel to the mounting region, and disposed spaced apart at different distances going out from the central region in a top-down view).
Regarding claim 13, Kim teaches the semiconductor package of claim 11, wherein the adhesive layer includes a non-conductive film (NCF) Fig. 4: adhesive is formed of a non-conductive film NCF; [0034]).
Regarding claim 15, Kim teaches the semiconductor package of claim 11, wherein the first semiconductor chip includes:
a first substrate (Fig. 4: first substrate 101; [0068]);
a first wiring layer on a first surface of the first substrate (Fig. 4: first semiconductor device layer 110 disposed on an underside of the first substrate 101 and containing first interconnection layer 120; [0068]),
the first wiring layer having a plurality of redistribution pads (Fig. 4: first connection pad 130 disposed on the underside and connected to the interconnection layer 120; [0024]);
a plurality of through electrodes penetrating the first substrate (Fig. 4: first through-electrode 150; [0068]); and
a plurality of first bonding pads respectively disposed on the plurality of redistribution pads (Fig. 4: first connection terminals 140 connected to the first connection pads 130), and
wherein the plurality of first measurement structures and the plurality of second measurement structures are electrically connected to the plurality of first bonding pads via at least one of the plurality of through electrodes of the first semiconductor chip and via the first wiring layer.
However, Nakagawa teaches wherein the plurality of first measurement structures and the plurality of second measurement structures are electrically connected to the plurality of first bonding pads via at least one of the plurality of through electrodes of the first semiconductor chip and via the first wiring layer (See annotated Fig. 2 and Fig. 3A-C: the interconnection layers are connected through vias to input/output pads 7).
It would have been obvious to one of ordinary skill in the art to combine the semiconductor package of Kim with the through vias of Nakagawa in order to connect the test region with the pads for electrical functionality testing of the semiconductor chip.
Regarding claim 16, Kim teaches the semiconductor package of claim 15, wherein the first semiconductor chip includes a plurality of second conductive bumps respectively disposed on the plurality of first bonding pads (Fig. 4: first connection terminals 140 disposed on upper surface pad 530, which is a ball structure; [0026]).
Regarding claim 17, Kim teaches the semiconductor package of claim 15, wherein
the first semiconductor chip has a second surface opposite to the first surface (Fig. 4: the upper surface of the semiconductor chip 100 with first bump pads 160; [0068] – [0070]),
the first semiconductor chip having a plurality of second bonding pads on the second surface (Fig. 4: first bump pads 160 disposed on the upper surface of semiconductor chip 100; [0068] – [0070]), wherein
the second semiconductor chip has a plurality of third bonding pads on a surface of the second semiconductor chip (Fig. 4: 240), wherein
the plurality of conductive bumps are respectively disposed between the plurality of second bonding pads and the plurality of third bonding pads(Fig. 4: second semiconductor chip 200 connects to the first semiconductor chip 100 through second connection terminal 240, which is equivalent to bump structure (BS) and can be a ball structure, and is electrically between second lower bump pad 230 and bond pad 160 of the first semiconductor chip; [0033] and [0068] – [0070]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Nakagawa as applied to claim 1 above, and further in view of Davis et al. (US 20030155642 A1; hereinafter Davis).
Regarding claim 4, Kim does not explicitly teach the semiconductor package of claim 1, wherein each of the plurality of first measurement structures comprises a metal line including copper (Cu).
Nakagawa teaches in Fig. 2 (see annotated Fig. 2), that the inter-chip connects 6 are parallel lines that run along the edge of the central region of the semiconductor chip 3. They are not explicitly taught however, to be made of metal, or specifically copper.
However, Davis teaches wherein each of the plurality of first measurement structures comprises a metal line including copper (Cu) (Fig. 4: metal lines 37 extend around the periphery of the chip 29 exterior to pads 3 are made of copper; [0026] and [0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the semiconductor package of Kim with the measurement structure of Nakagawa and the metal lines made of copper Davis in order to have a measurement structure that is conductive and can test the electrical functionality of the semiconductor chip.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Nakagawa as applied to claim 5 above, and further in view of Davis.
Regarding claim 7, Kim does not explicitly teach the semiconductor package of claim 5, wherein each of the plurality of second measurement structures comprises a metal line including copper (Cu).
Nakagawa teaches in Fig. 2 (see annotated Fig. 2) and paragraph 33, that inter-test pad interconnects 5 extend, are adjacent to, and connect the test pads 4 to the rest of the semiconductor chip 3. However, Nakagawa does not teach that these interconnects are made of metal, or more specifically copper.
However, Davis teaches wherein each of the plurality of second measurement structures comprises a metal line including copper (Cu) (Fig. 4: copper lines 38 extending out from pads 45; [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the semiconductor package of Kim with the measurement structures of Nakagawa using the materials of Davis in order to in order to have a measurement structure that is conductive and can test the electrical functionality of the semiconductor chip.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Nakagawa as applied to claim 11 above, and further in view of Davis.
Regarding claim 14, Kim does not explicitly teach the semiconductor package of claim 11, wherein each of the plurality of first measurement structures and each of the plurality of second measurement structures comprises a metal line including copper (Cu).
Nakagawa teaches in Fig. 2 (see annotated Fig. 2), that the inter-chip connects 6 are parallel lines that run along the edge of the central region of semiconductor chip 3. Nakagawa also teaches in Fig. 2 (see annotated Fig. 2) and paragraph 33, that inter-test pad interconnects 5 extend, are adjacent to, and connect the test pads 4 to the rest of the semiconductor chip 3. However, Nakagawa does not teach that these interconnects are made of metal, or more specifically copper.
However, Davis teaches (Fig. 4: metal lines 37 extend around the periphery of the chip 29 exterior to pads 3 are made of copper, and copper lines 38 extending out from pads 45; [0026], [0034, and [0036]).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Nakagawa and in further view of Kwon (US 20220384322 A1; hereinafter Kwon).
Regarding claim 18, Kim teaches a semiconductor package (Fig. 4: semiconductor package 40; [0064]), comprising:
a first semiconductor chip (Fig. 4: semiconductor chip 100; [0066]) including:
a first substrate (Fig. 4: first substrate 101; [0068]),
a plurality of through electrodes penetrating the first substrate (Fig. 4: first through-electrode 150; [0068]),
a first wiring layer on a first surface of the first substrate (Fig. 4: first semiconductor device layer 110 disposed on an underside of the first substrate 101 and containing first interconnection layer 120; [0068]),
the first wiring layer having a plurality of first redistribution pads (Fig. 4: first connection pad 130 disposed on the underside and connected to the interconnection layer 120; [0024]),
a plurality of first bonding pads respectively disposed on the plurality of first redistribution pads (Fig. 4: upper surface pad 530 connected to the first connection pads 130 through first connection terminals 140), and
a plurality of second bonding pads respectively disposed on a chip mounting region of a second surface opposite to the first surface of the first substrate (Fig. 4: mounting region is the upper surface of the semiconductor chip 100 with first bump pads 160; [0068] – [0070]);
a second semiconductor chip (Fig. 4: second semiconductor chip 200; [0069]) including:
a second substrate (Fig. 4: second substrate 201; [0069]),
a second wiring layer on a first surface of the second substrate (Fig. 4: a second semiconductor device layer 210 including a second interconnection layer 220; [0069]),
the second wiring layer having a plurality of second redistribution pads, and
a plurality of third bonding pads (Fig. 4: second connection terminal 240; [0069]) respectively disposed on the plurality of second redistribution pads,
the second semiconductor chip being mounted on the chip mounting region of the first semiconductor chip via a plurality of conductive bumps respectively disposed between the plurality of second bonding pads and the plurality of third bonding pads (Fig. 4: second semiconductor chip 200 connects to the first semiconductor chip 100 through second connection terminal 240, which is equivalent to bump structure (BS) and can be a ball structure, and is electrically between second lower bump pad 230 and bond pad 160 of the first semiconductor chip; [0033] and [0068] – [0070]);
a plurality of first measurement structures on the second surface of the first semiconductor chip parallel to edges of the chip mounting region, the plurality of first measurement structures being sequentially arranged to be spaced apart by a constant distance along a direction from an edge of the chip mounting region toward an edge of the first semiconductor chip that faces the edge of the chip mounting region,
a plurality of second measurement structures respectively disposed between ends of each edge of the chip mounting region to extend along a direction perpendicular to each edge of the chip mounting region;
an adhesive layer filling a gap between the first semiconductor chip and the second semiconductor chip (Fig. 4: non-conductive film NCF is an adhesive layer between the first and second semiconductor chips 100 and 200; [0034]),
the adhesive layer including a central portion on the chip mounting region (See annotated Fig. 4: non-conductive film NCF covers the entire semiconductor chip 100, including the mounting and edge regions, however is not explicit to the measurement structures) to contact at least one of the plurality of second measurement structures and
at least one overflow portion protruding from the chip mounting region to a test region surrounding the chip mounting region (See annotated Fig. 4: overflow portion surrounds the sides of the semiconductor chips, which includes an edge region) to contact at least one of the plurality of first measurement structures; and
a molding member on the second surface of the first semiconductor chip to cover side surfaces of the second semiconductor chip (Fig. 4: molding member 600 surrounding semiconductor chips 100 and 200; [0079]).
Nakagawa teaches the following limitations not explicitly taught by Kim:
a plurality of first measurement structures on the second surface of the first semiconductor chip parallel to edges of the chip mounting region (See zoomed in annotated Fig. 2 and Fig. 3-4: first measurement structures area interconnects 6 running along an edge of the chips central region)
the plurality of first measurement structures being sequentially arranged to be spaced apart by a constant distance along a direction from an edge of the chip mounting region toward an edge of the first semiconductor chip that faces the edge of the chip mounting region (see annotated Fig. 2 and Fig. 4A-C: inter-chip connects 6 connected to inter test-pad interconnects 5 are disposed spaced apart at different distances from the central region in a top-down view),
a plurality of second measurement structures respectively disposed between ends of each edge of the chip mounting region to extend along a direction perpendicular to each edge of the chip mounting region (See zoomed in annotated Fig. 2: test pads 4 disposed at the end of the edge of the chip mounting region and connected to inter-test pad interconnects 5 which extend inwards towards the central region, perpendicular to the edge).
Nakagawa also teaches in paragraph 3, that in a general manufacturing process for a semiconductor device, functionality tests are conducted in order to test the functions of a semiconductor chip formed on the semiconductor wafer before moving to a subsequent assembling steps.
It would have been to one of ordinary skill in the art to combine the semiconductor package of Kim with the measurement structures in an edge/test area of Nakagawa in order to test the functionality of the semiconductor chip before mounting the second chip, and to also cover the measurement structures with the adhesive NCF, either directly or indirectly, in order to electrically isolate the measurement structures that are no longer in use after manufacturing.
Kwon teaches the following limitations not explicitly taught by the combination of Kim and Nakagawa:
the second wiring layer having a plurality of second redistribution pads (Fig. 3C: upper substrate 710 may be a redistribution layer includes second metal pads 712), and
a plurality of third bonding pads respectively disposed on the plurality of second redistribution pads (Fig. 3C: first metal pad 711 coupled to the second metal pad 712 by connection to metal line 715; [0084]),
the second semiconductor chip being mounted on the chip mounting region of the first semiconductor chip via a plurality of conductive bumps respectively disposed between the plurality of second bonding pads and the plurality of third bonding pads (Fig. 3C: upper package 20 mounted onto lower package 10’ by connection from pad 650 to solder ball 750 and pad 711; [0082] – [0084]);
It would have been obvious to one of ordinary skill in the art to combine the semiconductor package of Kim with the redistribution pads of Kwon in order to electrically connect the semiconductor chips together through the pads, bump and redistribution layer.
Regarding claim 19, Kim teaches the semiconductor package of claim 18, wherein the adhesive layer includes a non-conductive film (NCF) (Fig. 4: adhesive is formed of a non-conductive film NCF; [0034]).
Regarding claim 20, Kim does not explicitly teach the semiconductor package of claim 18, wherein the plurality of first measurement structures and the plurality of second measurement structures are electrically connected to the plurality of first bonding pads via at least one of the plurality of through electrodes of the first semiconductor chip and via the first wiring layer.
However, Nakagawa teaches wherein the plurality of first measurement structures and the plurality of second measurement structures are electrically connected to the plurality of first bonding pads via at least one of the plurality of through electrodes of the first semiconductor chip and via the first wiring layer (See annotated Fig. 2 and Fig. 3A-C: the interconnection layers are connected through vias to input/output pads 7).
It would have been obvious to one of ordinary skill in the art to combine the semiconductor package of Kim with the through vias of Nakagawa in order to connect the test region with the pads for electrical functionality testing of the semiconductor chip.
Conclusion
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/BENJAMIN HOANG TRAN/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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