Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species B in the reply filed on 12/26/2025 is acknowledged.
Claims 7-10 and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/26/2025.
Claim Objections
Claim 1 is objected to because of the following informalities: the claim recites “a corresponding row” in line 16, which appears to be “the corresponding row”. Appropriate correction is required.
Claims 2-6 and 11 are objected based on their dependence from claim 1.
Claim 19 is objected to because of the following informalities: the claim recites “a corresponding row” in line 16, which appears to be “the corresponding row”. Appropriate correction is required.
Claim 20 is objected based on its dependence from claim 19.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xiang et al. (US 2017/0301286).
Regarding claim 1, Xiang discloses a display device (see device 600 in Fig. 6; para[0076]) comprising:
a plurality of sub-pixel circuits disposed in a matrix form including a plurality of rows and a plurality of columns (see sub-pixel circuits in Figs. 4A and 4B disposed in a matrix as shown e.g. in Fig. 3B);
a plurality of light emitting elements respectively connected to the plurality of sub-pixel circuits (see light-emitting diodes OL in Figs. 4A and 4B);
a plurality of output lines configured to carry a data signal to the plurality of subpixel circuits (see data voltage signal lines Vdata in Figs. 3B and 4A-4B); and
a plurality of first scan lines and a plurality of second scan lines configured to carry a scan signal to the plurality of sub-pixel circuits (see in Fig. 3B first control signal lines S11 to Sn1 and second control signal lines S12 to Sn2 which provide control signal inputs to each sub-pixel circuit; para[0050]-para[0052]; para[0057]),
wherein each of the plurality of output lines is commonly connected to sub-pixel circuits, among the plurality of sub-pixel circuits, disposed in different columns among the plurality of columns (see in Fig. 3B “the pixel driving circuits in any pixel column of the pixel array and a pixel column adjacent to the pixel column share one data voltage signal line“; para[0057]),
each of the plurality of first scan lines is connected to first sub-pixel circuits of a corresponding row among the plurality of sub-pixel circuits (see in Fig. 3B each of first control signal lines S11 to Sn1 is connected to first sub-pixel circuits of a corresponding row), and
each of the plurality of second scan lines is connected to second sub-pixel circuits of a corresponding row among the plurality of sub-pixel circuits (see in Fig. 3B each of second control signal lines S12 to Sn2 is connected to second sub-pixel circuits of the corresponding row), wherein the first sub-pixel circuits and the second sub-pixel circuits are alternately disposed in the corresponding row (see in Fig. 3B, the first sub-pixel circuits and the second sub-pixel circuits are alternately disposed in the corresponding row).
Regarding claim 2, Xiang discloses all the claim limitations as applied above (see claim 1). In addition, Xiang discloses a data driver outputting the data signal to the plurality of sub-pixel circuits through the plurality of output lines (regarding Fig. 6, note that since “the organic light-emitting display device 600 comprises the organic light-emitting display panel of the… embodiments”, it is clear that it necessarily comprises “known structures” such as a data driver that outputs the data signals to the plurality of sub-pixel circuits through data voltage signal lines Vdata in Figs. 3B and 4A-4B; para[0076]); and
a scan driver outputting the scan signal to the plurality of sub-pixel circuits through the plurality of first scan lines and the plurality of second scan lines (see e.g. scan driver 510 in Fig. 5A, necessarily included in the organic light-emitting display device 600 of Fig. 6; para[0070]; para[0076]),
wherein the plurality of rows include m rows and the plurality of columns includes n columns (see e.g. in Figs. 3B four rows (m=4) and six columns (n=6)),
a number of the plurality of first scan lines is m, a number of the plurality of second scan lines is m, the number of the plurality of output lines is n/2 (see e.g. in Fig. 3B a number of first control signal lines S11 to Sn1 being four for four rows, a number of second control signal lines S12 to Sn2 being four for four rows, and a number of data voltage signal lines Vdata being three for six columns),
during a horizontal period corresponding to a selected row among the plurality of rows, the scan driver activates a voltage of a first scan line corresponding to the selected row among the plurality of first scan lines during a first period of the horizontal period (see in Fig. 8 period T11+T12 during which a high level signal is provided by the scan driver to activate the first control signal line S1 of a selected row; para[0067]; para[0088]-para[0089]), and activates a voltage of a second scan line corresponding to the selected row of the plurality of second scan lines during a second period different from the first period of the horizontal period (see in Fig. 8 period T13+T14 during which a high level signal is provided by the scan driver to activate the second control signal line S2 of the selected row; para[0068]; para[0090]-para[0091]), and m and n are integers greater than or equal to 2 (e.g. m=4 and n=6, as indicated above).
Regarding claim 3, Xiang discloses all the claim limitations as applied above (see claim 2). In addition, Xiang discloses during the first period, the data signal output to the plurality of output lines is applied to a first sub-pixel circuit among the first sub-pixel circuits corresponding to the selected row (regarding Figs. 3B, 4B and 8, during period T12 included in period T11+T12, the data signal is provided through the data voltage signal line Vdata (e.g., the data voltage signal line Vdata[i]/Vdata[i+1] in FIG. 4B) to first sub-pixel circuit 440 of the selected row; para[0067]; para[0088]-para[0089]), and during the second period, the data signal output to the plurality of output lines is applied to a second sub-pixel circuit among the second sub-pixel circuits corresponding to the selected row (regarding Figs. 3B, 4B and 8, during period T14 of period T13+T14, the data signal is provided through the data voltage signal line Vdata (e.g., the data voltage signal line Vdata[i]/Vdata[i+1] in FIG. 4B) to second sub-pixel circuit 430 of the selected row; para[0068]; para[0090]-para[0091]).
Regarding claim 12, Xiang discloses a display device (see device 600 in Fig. 6; para[0076]) comprising:
a data driver outputting data to k output lines (regarding Fig. 6, note that since “the organic light-emitting display device 600 comprises the organic light-emitting display panel of the… embodiments”, it is clear that it necessarily comprises “known structures” such as a data driver that outputs data signals to the plurality of sub-pixel circuits in Figs. 3B and 4A-4B through data voltage signal lines Vdata; see e.g. three data voltage signal lines Vdata in Fig. 3B; para[0076]);
a scan driver outputting a scan signal to m first scan lines and m second scan lines (see e.g. scan driver 510 in Fig. 5A, necessarily included in the organic light-emitting display device 600 of Fig. 6, to output control signals to first control signal lines S11 to SM1 and second control signal lines S12 to SM2, or first control signal lines S11 to Sn1 and second control signal lines S12 to Sn2 in Fig. 3B, that is, to e.g. four first control signal lines and to e.g. four second control signal lines; para[0070]; para[0076]); and
a pixel unit connected to the k output lines, first scan lines, and second scan lines (see e.g. pixel unit in Fig. 3B connected to three data voltage signal lines Vdata, first control signal lines S11 to Sn1 and second control signal lines S12 to Sn2), wherein the pixel unit comprises:
a plurality of sub-pixel circuits disposed in a matrix form including m rows and 2k columns (see sub-pixel circuits in Figs. 4A and 4B disposed in a matrix including e.g. four rows and six columns, as shown e.g. in Fig. 3B),
a plurality of light emitting elements respectively connected to the plurality of sub-pixel circuits (see light-emitting diodes OL in Figs. 4A and 4B),
wherein an h-th output line among the k output lines is commonly connected to sub-pixel circuits positioned in a (2h-1)-th column and a 2h-th column among the plurality of sub-pixel circuits (see in Fig. 3B “the pixel driving circuits in any pixel column of the pixel array and a pixel column adjacent to the pixel column share one data voltage signal line“; para[0057]),
an i-th first scan line among the first scan lines is connected to first sub-pixel circuits among sub-pixel circuits positioned in an i-th row (see in Fig. 3B each of first control signal lines S11 to Sn1 is connected to first sub-pixel circuits of a corresponding row),
an i-th second scan line among the second scan lines is connected to second subpixel circuits among the sub-pixel circuits positioned in the i-th row (see in Fig. 3B each of second control signal lines S12 to Sn2 is connected to second sub-pixel circuits of the corresponding row), wherein the first sub-pixel circuits and the second sub-pixel circuits are alternately disposed in the i-th row (see in Fig. 3B, the first sub-pixel circuits and the second sub-pixel circuits are alternately disposed in the corresponding row), and
m and n are integers greater than or equal to 2 (see in Fig. 3B m and n are e.g. 4), k is an integer greater than or equal to 1 (see in Fig. 3B k is e.g. 3), h is an integer greater than 0 and less than or equal to k (see in Fig. 3B h is e.g. an integer greater than 0 and less than or equal to e.g. 3), and i is an integer greater than 0 and less than or equal to m (see in Fig. 3B i is e.g. an integer greater than 0 and less than or equal to e.g. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6, 11, 13-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xiang et al. (US 2017/0301286), in view of Tian et al. (US 2024/0298494).
Regarding claim 4, Xiang discloses all the claim limitations as applied above (see claim 3). However, Xiang does not appear to expressly disclose the data driver is configured to apply the data signal corresponding to a first color to sub-pixel circuits connected to a first output line among the plurality of output lines.
Tian discloses applying a data signal corresponding to a first color to sub-pixel circuits connected to a first output line among a plurality of output lines (“The pixel driving circuitries in a same column are electrically coupled to a same data line, the data line is configured to provide a data voltage corresponding to a same color, and the pixel driving circuitries electrically coupled to the same data line correspond to the color”; see e.g. in Fig. 18, data line D1 is provided with and applies a data signal of blue color to pixel driving circuits P11, P21, P31 and P41; para[0042]; para[0073]-para[0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Xiang’s invention, with the teachings in Tian’s invention, to have the data driver is configured to apply the data signal corresponding to a first color to sub-pixel circuits connected to a first output line among the plurality of output lines, for the advantage of a configuration that provides a consistent drive voltage, and reduces power consumption (para[0043]).
Regarding claim 5, Xiang and Tian disclose all the claim limitations as applied above (see claim 4). In addition, Tian discloses applying the data signal corresponding to a second color to sub-pixel circuits connected to a second output line among the plurality of output lines (“The pixel driving circuitries in a same column are electrically coupled to a same data line, the data line is configured to provide a data voltage corresponding to a same color, and the pixel driving circuitries electrically coupled to the same data line correspond to the color”; see e.g. in Fig. 18, data line D2 is provided with and applies a data signal of green color to pixel driving circuits P12, P22, P32 and P42; para[0042]; para[0073]-para[0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the data driver is configured to apply data-the data signal corresponding to a second color to sub-pixel circuits connected to a second output line among the plurality of output lines, as also taught by Tian, for the advantage of providing a consistent drive voltage, and reducing power consumption (para[0043]).
Regarding claim 6, Xiang discloses all the claim limitations as applied above (see claim 1). In addition, Xiang discloses the plurality of light emitting elements are formed on the plurality of sub-pixel circuits (see light-emitting diodes OL formed on the sub-pixel circuits in Figs. 4A and 4B). However, Xiang does not appear to expressly disclose an anode electrode connecting a light emitting element among the plurality of light emitting elements and a corresponding sub-pixel circuit is disposed on at least two sub-pixel circuits of the plurality of sub-pixel circuits.
Tian discloses an anode electrode connecting a light emitting element among a plurality of light emitting elements and a corresponding sub-pixel circuit is disposed on at least two sub-pixel circuits of a plurality of sub-pixel circuits (see in Figs. 10-11, the claimed anode comprising e.g. B13 and L2, connecting from the third column to the first column a corresponding light-emission element to a corresponding pixel driving circuitry, is disposed on at least two pixel driving circuitries of the plurality of pixel driving circuitries; para[0042]; para[0046]; para[0061]-para[0063]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Xiang’s invention, with the teachings in Tian’s invention, to have an anode electrode connecting a light emitting element among the plurality of light emitting elements and a corresponding sub-pixel circuit is disposed on at least two sub-pixel circuits of the plurality of sub-pixel circuits, for the advantage of using a conventional light-emission elements arrangement in a configuration that simultaneously provides a consistent drive voltage, and reduces power consumption (para[0003]; para[0043]).
Regarding claim 11, Xiang discloses all the claim limitations as applied above (see claim 1). However, Xiang does not appear to expressly disclose the plurality of light emitting elements are disposed in one of an RGBG structure or an RGB stripe structure.
Tian discloses a plurality of light emitting elements are disposed in one of an RGBG structure or an RGB stripe structure (para[0073]; see a plurality of light emitting elements are disposed in an RGBG structure).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Xiang’s invention, with the teachings in Tian’s invention, to have the plurality of light emitting elements are disposed in one of an RGBG structure or an RGB stripe structure, for the advantage of using a conventional light-emission elements arrangement while simultaneously providing a consistent drive voltage, and reducing power consumption (para[0003]; para[0043]).
Regarding claim 13, Xiang discloses all the claim limitations as applied above (see claim 12). In addition, Xiang discloses the data driver is configured to apply the data signal during a plurality of horizontal periods to sub-pixel circuits connected to each of at least one output line among the k output lines (regarding Figs. 3B, 4B and 8, during period T12 included in period T11+T12, data signal is provided through each corresponding data voltage signal line Vdata (e.g., the data voltage signal line Vdata[i]/Vdata[i+1] in FIG. 4B) to first sub-pixel circuit 440 of a selected row, and during period T14 of period T13+T14, the data signal is provided through each corresponding data voltage signal line Vdata (e.g., the data voltage signal line Vdata[i]/Vdata[i+1] in FIG. 4B) to second sub-pixel circuit 430 of the selected row; para[0067]-para[0068]; para[0088]-para[0091]). However, Xiang does not appear to expressly disclose applying the data signal corresponding to a same color to sub-pixel circuits connected to each of at least one output line among the k output lines.
Tian discloses applying a data signal corresponding to a same color to sub-pixel circuits connected to each of at least one output line among k output lines (“The pixel driving circuitries in a same column are electrically coupled to a same data line, the data line is configured to provide a data voltage corresponding to a same color, and the pixel driving circuitries electrically coupled to the same data line correspond to the color”; see e.g. in Fig. 18, each data line D is provided with and applies a data signal of a corresponding color to corresponding pixel driving circuits P connected to each data line D; para[0042]; para[0073]-para[0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Xiang’s invention, with the teachings in Tian’s invention, to apply the data signal corresponding to a same color during a plurality of horizontal periods to sub-pixel circuits connected to each of at least one output line among the k output lines, for the advantage of a configuration that provides a consistent drive voltage, and reduces power consumption (para[0043]).
Regarding claim 14, Xiang and Tian disclose all the claim limitations as applied above (see claim 13). In addition, Xiang discloses the plurality of light emitting elements are formed on the plurality of sub-pixel circuits (see light-emitting diodes OL formed on the sub-pixel circuits in Figs. 4A and 4B).
In addition, Tian discloses an anode electrode connecting a light emitting element among a plurality of light emitting elements and a corresponding sub-pixel circuit is disposed on a sub-pixel circuit of the plurality of sub-pixel circuits that is not connected to the light emitting element (see in Figs. 10-11, the claimed anode comprising e.g. B13 and L2, connecting from the third column to the first column a corresponding blue light-emission element to a corresponding pixel driving circuitry, is disposed on a pixel driving circuitry of the plurality of pixel driving circuitries that is not connected to the blue light-emission element, e.g. disposed on the pixel driving circuitry corresponding to G12; para[0042]; para[0046]; para[0061]-para[0063]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have an anode electrode connecting a light emitting element among the plurality of light emitting elements and a corresponding sub-pixel circuit is disposed on a sub-pixel circuit of the plurality of sub-pixel circuits that is not connected to the light emitting element, as also taught by Tian, for the advantage of using a conventional light-emission elements arrangement in a configuration that simultaneously provides a consistent drive voltage, and reduces power consumption (para[0003]; para[0043]).
Regarding claim 15, Xiang and Tian disclose all the claim limitations as applied above (see claim 13). In addition, Xiang discloses the data driver is configured to apply the data signal during a plurality of horizontal periods to sub-pixel circuits connected to each of the k output lines (regarding Figs. 3B, 4B and 8, during period T12 included in period T11+T12, data signal is provided through each corresponding data voltage signal line Vdata (e.g., the data voltage signal line Vdata[i]/Vdata[i+1] in FIG. 4B) to first sub-pixel circuit 440 of a selected row, and during period T14 of period T13+T14, the data signal is provided through each corresponding data voltage signal line Vdata (e.g., the data voltage signal line Vdata[i]/Vdata[i+1] in FIG. 4B) to second sub-pixel circuit 430 of the selected row; para[0067]-para[0068]; para[0088]-para[0091]).
In addition, Tian discloses applying the data signal corresponding to the same color to sub-pixel circuits connected to each of the k output lines (“The pixel driving circuitries in a same column are electrically coupled to a same data line, the data line is configured to provide a data voltage corresponding to a same color, and the pixel driving circuitries electrically coupled to the same data line correspond to the color”; see e.g. in Fig. 18, each data line D is provided with and applies a data signal of a corresponding color to corresponding pixel driving circuits P connected to each data line D; para[0042]; para[0073]-para[0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to apply the data signal corresponding to the same color during a plurality of horizontal periods to sub-pixel circuits connected to each of the k output lines, for the advantage of a configuration that further provides a consistent drive voltage, and reduces power consumption (para[0043]).
Regarding claim 16, Xiang and Tian disclose all the claim limitations as applied above (see claim 15). In addition, Xiang discloses the plurality of light emitting elements are formed on the plurality of sub-pixel circuits (see light-emitting diodes OL formed on the sub-pixel circuits in Figs. 4A and 4B).
In addition, Tian discloses an anode electrode connecting a light emitting element among the plurality of light emitting elements and a corresponding sub-pixel circuit is disposed on at least two sub-pixel circuits of the plurality of sub-pixel circuits that are not connected to the light emitting element (see in Figs. 10-11, the claimed anode comprising e.g. B13 and L2, connecting from the third column to the first column a corresponding blue light-emission element to a corresponding pixel driving circuitry, is disposed on at least two sub-pixel driving circuitries of the plurality of pixel driving circuitries that are not connected to the blue light-emission element, e.g. disposed on the pixel driving circuitry corresponding to G12 and on the pixel driving circuitry below G12; para[0042]; para[0046]; para[0061]-para[0063]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have an anode electrode connecting a light emitting element among the plurality of light emitting elements and a corresponding sub-pixel circuit is disposed on at least two sub-pixel circuits of the plurality of sub-pixel circuits that are not connected to the light emitting element, as also taught by Tian, for the advantage of using a conventional light-emission elements arrangement in a configuration that simultaneously provides a consistent drive voltage, and reduces power consumption (para[0003]; para[0043]).
Regarding claim 18, Xiang discloses all the claim limitations as applied above (see claim 12). However, Xiang does not appear to expressly disclose the plurality of light emitting elements are disposed in one of an RGBG structure or RGB stripe structure.
Tian discloses a plurality of light emitting elements are disposed in one of an RGBG structure or an RGB stripe structure (para[0073]; see a plurality of light emitting elements are disposed in an RGBG structure).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Xiang’s invention, with the teachings in Tian’s invention, to have the plurality of light emitting elements are disposed in one of an RGBG structure or an RGB stripe structure, for the advantage of using a conventional light-emission elements arrangement while simultaneously providing a consistent drive voltage, and reducing power consumption (para[0003]; para[0043]).
Regarding claim 19, Xiang discloses a display device (see device 600 in Fig. 6; para[0076]) comprising:
a plurality of sub-pixel circuits disposed in a matrix form including a plurality of rows and a plurality of columns (see sub-pixel circuits in Figs. 4A and 4B disposed in a matrix as shown e.g. in Fig. 3B);
a plurality of light emitting elements respectively connected to the plurality of sub-pixel circuits (see light-emitting diodes OL in Figs. 4A and 4B);
a data driver outputting a data signal to the plurality of sub-pixel circuits through a plurality of output lines (regarding Fig. 6, note that since “the organic light-emitting display device 600 comprises the organic light-emitting display panel of the… embodiments”, it is clear that it necessarily comprises “known structures” such as a data driver that outputs data signals to the plurality of sub-pixel circuits in Figs. 3B and 4A-4B through data voltage signal lines Vdata; para[0076]); and
a scan driver outputting a scan signal to the plurality of sub-pixel circuits through a plurality of first scan lines and a plurality of second scan lines (see e.g. scan driver 510 in Fig. 5A, necessarily included in the organic light-emitting display device 600 of Fig. 6, to output control signals to first control signal lines S11 to SM1 and second control signal lines S12 to SM2, or first control signal lines S11 to Sn1 and second control signal lines S12 to Sn2 in Fig. 3B; para[0070]; para[0076]);
wherein each output line among the plurality of output lines is commonly connected to sub-pixel circuits of the plurality of sub-pixel circuits positioned in adjacent columns among the plurality of columns (see in Fig. 3B “the pixel driving circuits in any pixel column of the pixel array and a pixel column adjacent to the pixel column share one data voltage signal line“; para[0057]),
each of the plurality of first scan lines is connected to first sub-pixel circuits of a corresponding row among the plurality of sub-pixel circuits (see in Fig. 3B each of first control signal lines S11 to Sn1 is connected to first sub-pixel circuits of a corresponding row),
each of the plurality of second scan lines is connected to second sub-pixel circuits of a corresponding row among the plurality of sub-pixel circuits (see in Fig. 3B each of second control signal lines S12 to Sn2 is connected to second sub-pixel circuits of the corresponding row), wherein the first sub-pixel circuits and the second sub-pixel circuits are alternately disposed in the corresponding row (see in Fig. 3B, the first sub-pixel circuits and the second sub-pixel circuits are alternately disposed in the corresponding row).
However, Xiang does not appear to expressly disclose an anode electrode connecting a light emitting element among the plurality of light emitting elements and a corresponding sub-pixel circuit is disposed on a sub-pixel circuit of the plurality of sub-pixel circuits that is not connected to the light emitting element.
Tian discloses an anode electrode connecting a light emitting element among a plurality of light emitting elements and a corresponding sub-pixel circuit is disposed on a sub-pixel circuit of a plurality of sub-pixel circuits that is not connected to the light emitting element (see in Figs. 10-11, the claimed anode comprising e.g. B13 and L2, connecting from the third column to the first column a corresponding blue light-emission element to a corresponding pixel driving circuitry, is disposed on a pixel driving circuitry of a plurality of pixel driving circuitries that is not connected to the blue light-emission element, e.g. disposed on the pixel driving circuitry corresponding to G12; para[0042]; para[0046]; para[0061]-para[0063]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Xiang’s invention, with the teachings in Tian’s invention, to have an anode electrode connecting a light emitting element among the plurality of light emitting elements and a corresponding sub-pixel circuit is disposed on a sub-pixel circuit of the plurality of sub-pixel circuits that is not connected to the light emitting element, for the advantage of using a conventional light-emission elements arrangement in a configuration that simultaneously provides a consistent drive voltage, and reduces power consumption (para[0003]; para[0043]).
Regarding claim 20, Xiang and Tian disclose all the claim limitations as applied above (see claim 19). In addition, Tian discloses the anode electrode connecting the light emitting element and the corresponding sub-pixel circuit is disposed on at least two sub-pixel circuits of the plurality of sub-pixel circuits that are not connected to the light emitting element (see in Figs. 10-11, the claimed anode comprising e.g. B13 and L2, connecting from the third column to the first column the corresponding blue light-emission element to the corresponding pixel driving circuitry, is disposed on at least two sub-pixel driving circuitries of the plurality of pixel driving circuitries that are not connected to the blue light-emission element, e.g. disposed on the pixel driving circuitry corresponding to G12 and on the pixel driving circuitry below G12; para[0042]; para[0046]; para[0061]-para[0063]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the anode electrode connecting the light emitting element and the corresponding sub-pixel circuit is disposed on at least two sub-pixel circuits of the plurality of sub-pixel circuits that are not connected to the light emitting element, as also taught by Tian, for the advantage of using a conventional light-emission elements arrangement in a configuration that simultaneously provides a consistent drive voltage, and reduces power consumption (para[0003]; para[0043]).
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GLORYVID FIGUEROA-GIBSON whose telephone number is (571)272-5506. The examiner can normally be reached on 9am-5pm, Monday -Friday, Eastern Time.
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/GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623