DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 and 11-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Beukema et al. (USPN 8,599,966) in view of Zhou et al. (USPN 10,014,036).
With respect to claim 1, Beukema et al discloses, in Fig. 3, a receiver circuit with adaptive biasing (Fig. 3) comprising:
an-die termination network (TERM/302, on the same chip/die, see Col. 3 lines 62-67) coupled to a receiver input (332);
a potential equalizer coupled to the differential receiver input (314, 312, 310 and 316) and the on-die termination network (at 332), the potential equalizer comprising a biased voltage divider (314 with 312) and an equalized bias node (node between 310, 316 and 340) a receive driver comprising an input coupled to the equalized bias node (306);
a receive driver (306) comprising an input (e.g. non-inverting terminal) coupled to the equalized bias node (node between 310, 316 and 340) and
a feedback circuit loop (340, 336, 334, 316 and 330. The above elements construct a feedback loop in that 336 monitors the voltage at the “equalized bias node” and controls/adjusts the voltage at the “equalized bias node” to be equal to Vr via the feedback from 336 to 334 to 330 back to the “equalized bias node” via both 316 and 314 with 312 and 310) coupled to the equalized bias node at one end (at the input of 340/non-inverting terminal of 336) and to a node in the biased voltage divider at the other (node between 314 with 312 via the output of 334/330).
Beukema et al. discloses the receiver of Fig. 3 being a differential receiver and thus fails to disclose the receiver input terminal being a “single-ended” input. Nevertheless it is old and well-known to replace differential receivers with single-ended receivers and vice versa. Furthermore, it is known the use single-ended receivers in place of differential receiver, since single-ended receivers are less complex, use less circuitry and consume less power compared to differential receivers. This is further evidenced in Col. 8 lines 26-38 of Zhou et al.
It would have been obvious to replace the differential receiver with a single-ended receiver for the purpose of reducing area, complexity and power consumption of the receiver circuit as evidenced by Zhou et al.
It is noted that Zhou et al. also anticipates on-die termination (see 76 of Fig. 8 and Col. 4 line 66 to Col. 5 line 3)
With respect to claim 2, the receiver circuit according to claim 1, wherein:
the feedback circuit loop generates a current control signal (output of 330); and the current control signal is injected into a node of the biased voltage divider (node between 314 and 312).
With respect to claim 3, the receiver circuit according to claim 2, wherein the feedback circuit loop adjusts a bias voltage at the equalized bias node based on the current control signal (330 is connected and operative with 314 and 312 as claimed).
With respect to claim 4, the receiver circuit according to claim 1, wherein: the potential equalizer further comprises an inline resistor-capacitor (RC) network coupled to the single-ended receiver input (310 with 316); and
the equalized bias node is positioned between the RC network and the biased voltage divider (via the node connected to 316, 314 and 312 and through Rb and/or between the node connected to 312 and 310 through 310).
With respect to claim 5, Beukema et al. discloses, the feedback circuit loop comprises a difference amplifier (336), a controller (334), and a current converter (330).
Beukema et al. merely discloses a generic controller (334) and a current adjusting circuit (330) under control of the generic controller.
Beukema et al. fails to disclose the specifics of 334 and how 330 is controlled by 334. Thus, Beukema et al. fails to disclose “an analog-to-digital converter, and a digital-to-current converter”. However, it is old and well-known that controllers, such as 334, may be constructed from either analog devices or from digital devices such as processors, CPUs, microcontrollers, etc. Digital control devices have at least one advantage over analog control devices in that digital controllers, such as a processor, can be easily modified, tuned and tested through the use of firmware updates and the like by programming the digital controllers to operate as desired by the user/designer. Examiner takes official notice that it is old and well-known to construct control circuits using digital control devices. Furthermore, when digital controllers are used in mixed analog and digital system (such as the analog signals input/output to/from 334 of Beukema et al.) a conversion from the analog domain to a digital domain using an analog to digital converter is required. Furthermore, a conversion from the digital domain to the analog domain is required to interface between the analog and digital domains. Examiner takes official notice of such analog to digital converters and digital to analog converters between the digital and analog domains.
It would have been obvious to use a digital controller as the controller of 334 of Beukema et al. for the purpose of having a controller with increased flexibility that can be easily modified, tuned and tested through the use of firmware updates and the like by programming the digital controllers to operate as desired by the user/designer. Furthermore, it would have been obvious to add an analog to digital converter within 334 between the analog domain (e.g., output of 336) and the digital domain (e.g., input/internal to 334) and a digital to analog converter within 334 between the digital domain (e.g., output of 334) and the analog domain (e.g., input of 330), for the purpose of allowing a digital controller to interface with the analog circuitry of Beukema et al.
As modified above Beukema et al. includes an analog-to-digital converter (between output of 336 and input of 334), and a digital-to-current converter (i.e., digital to analog converter at the output of 334 to 330 with 330 of Beukema et al.).
With respect to claim 6, the receiver circuit according to claim 5, wherein the feedback circuit loop further comprises a filter between the equalized bias node and the difference amplifier (capacitor connected to the non-inverting terminal of 336).
With respect to claim 7, the receiver circuit according to claim 5, wherein the difference amplifier outputs a difference voltage (output of 336) based on a difference between a reference voltage (Vr) and a bias voltage at the equalized bias node (via 340).
With respect to claim 8, the receiver circuit according to claim 7, wherein the analog-to-digital converter converts the difference voltage from the difference amplifier to a digital difference value (as modified above the analog to digital converter between 336 and 334 operates as claimed).
With respect to claim 9, the receiver circuit according to claim 8, wherein:
the digital-to-current converter converts the digital difference value to a current control signal (output of 330 based on the digital to analog converter output from 334 and the processing of 334); and
the current control signal is injected into a node of the biased voltage divider (output of 330 to the node between 314 and 312).
Claims 11-19 are rejected for essentially the same reasons claims 1-9 above.
Allowable Subject Matter
Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 12/17/2025 have been fully considered but they are not persuasive.
With respect to the argument that Beukema et al. fails to disclose a “single ended” input. Examiner agrees with Applicant that Beukema et al. merely discloses a differential input and not a single ended input. However, it can be seen that Zhou discloses that one may construct a receiver using either a single ended or a differential topology. Zhou further discloses that differential amplifiers are more complex and increase silicon area (see Col. 8 lines 26-38) when compared to smaller single ended receivers (see Col. 8 lines 39-49). Furthermore, it is old and well-known to replace differential receiver with single ended receivers. This is further evidenced by Boecker et al. (USPN 7,280,590) in Fig. 5 (differential) and Fig. 4 (single ended) and Zhuang et al. (USPN 8,319,579) see Col. 7 lines 44-48 . Moreover, Singh et al. further evidences that there is a design tradeoff between operational speeds and the cost of extra circuit elements (pins, traces, etc.) between differential receivers and single-ended receivers (see Col. 3 line 62 to Col 4 line 3). Thus, it is old and well-known that one may design a circuit topology using either differential receivers or single ended receivers according to desired design parameters. Thus, the combination of Beukema et al. and Zhou disclose such a single-ended receiver circuit. Using such single-ended devices in place of differential devices is old and well-known.
The argument that “the bias control process 334 and resistor divider 312 and 314 of Beukema are not part of ‘a feedback circuit loop coupled to ... a node in the biased voltage divider’ according to claim 11”, since “bias control process 334 and resistor divider 312 and 314 are part of a feedforward circuit and not feedback circuit loop” is not persuasive. While Beukema et al. states that Rd and Rff are part of a “feedforward circuit” that is not to say that R40, 336, 334, 330, 316 and Rff do not create a feedback loop. It is noted that the “FEEEDFORWARD GAIN CONTORL” (e.g., 322) construct the “feedforward circuit”, wherein the impedance/resistance of 314 and 312 are control by 322. Furthermore, a feedback loop is constructed by the input of 336 being connected to the “equalized bias node” via 340. Amplifier 336 controls 334 which in turn controls 330 to supply a current to both 312 and 316 that provide a feedback path back to the “equalized bias node”. This feedback loop can be seen in the Markup of Fig. 3 of Beukema et al. below. Thus a feedback loop that is connected as claimed is included within the circuitry of Beukema et al.
Markup of Fig. 3 of Beukema et al.
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2849