DETAILED ACTION
This office action is in response to the application on 8/9/2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/9/2024 and 3/7/2025 are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
It is unclear to the examiner regarding the limitation recited by the applicant reciting “wherein the conductive pattern of the second redistribution substrate comprises a wiring pattern and a via pattern forming a single body or structure having a character “T” shape…”
Claim 6 recites the limitation " the conductive pattern of the second redistribution substrate” in the first line of the claim. There is insufficient antecedent basis for this limitation in the claim. There is no mention of a conductive pattern of the second redistribution substrate in preceding claim 1. Appropriate correction is required. For purpose of examination, the examiner has interpreted the claim to read “wherein a conductive pattern of the second redistribution substrate comprises a wiring pattern and a via pattern forming a single body or structure having a character “T” shape…”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Min (US 2020/0294964) in view of Yu (US 2021/0098381).
With respect to Claim 1, Min discloses (Fig 8-17) most aspects of the current invention including a method of manufacturing a semiconductor package, comprising:
forming device layers that comprises:
forming a die (3), which comprises a base layer (30), a circuit layer (36) on the base layer, and a via (35) provided to penetrate the base layer and coupled to the circuit layer; (Fig 10)
forming a pad (38) on the circuit layer of the die, the pad being coupled to the circuit layer; (Fig 10)
placing the die on a carrier substrate (82) such that the base layer faces the carrier substrate; (Fig 10)
coating the carrier substrate with a molding material (5) to form a molding portion encapsulating the die; (Fig 13)
performing a planarization process on the molding portion to expose the pad; (Fig 14)
removing the carrier substrate to expose the base layer; (method step carried out in Fig 12)
bonding a first device layer of the device layers to a first redistribution substrate (64) such that the pad of the first device layer is coupled to the first redistribution substrate; (Fig 15)
stacking a second device layer (6) of the device layers on the first device layer.
wherein the pad (38) of the first device layer is between the die (3) of the first device layer and the first redistribution substrate (64),
wherein the first redistribution substrate (64) comprises an insulating pattern (65) and a conductive pattern (16/66) in the insulating pattern to be in contact with the pad of the first device layer
However, Min does not disclose forming a second redistribution substrate the molding portion and the base layer of the second device layer and forming a penetration electrode to penetrate the molding portions of the device layers in a region around the dies of the device layers and to be coupled to the first redistribution substrate.
On the other hand, and in the same field of endeavor, Yu teaches (Fig 1-10,14) a method of manufacturing a semiconductor package, comprising forming device layers that comprises a die (130A), which comprises a base layer (131), a circuit layer (132) on the base layer, and a via (136) provided to penetrate the base layer and coupled to the circuit layer, forming a pad (134) on the circuit layer of the die, the pad being coupled to the circuit layer, bonding a first device layer (130A) of the device layers to a first redistribution substrate (220) such that the pad of the first device layer is coupled to the first redistribution substrate, stacking a second device layer (130B) of the device layers on the first device layer, forming a penetration electrode (120) to penetrate the molding portions (140) of the device layers in a region around the dies of the device layers and to be coupled to the first redistribution substrate, forming a second redistribution substrate (170/180) the molding portion and the base layer of the second device layer. Yu teaches the penetration electrode are used to provide electrical connection between the first redistribution substrate and the second redistribution substrate and further to allow direct metal-to-metal bonding to be achieved even if misalignment occurs, thereby ensuring the reliability of electrical connections between the integrated circuit components.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have method steps of forming a second redistribution substrate the molding portion and the base layer of the second device layer and forming a penetration electrode to penetrate the molding portions of the device layers in a region around the dies of the device layers and to be coupled to the first redistribution substrate, in the method of Min, as taught by Yu because the penetration electrode are used to provide electrical connection between the first redistribution substrate and the second redistribution substrate and further to allow direct metal-to-metal bonding to be achieved even if misalignment occurs, thereby ensuring the reliability of electrical connections between the integrated circuit components.
With respect to Claim 2, Yu teaches (Fig 14) wherein, at an interface of the first redistribution substrate and the pad of the first device layer, the conductive pattern (see metal 240) of the first redistribution substrate and the pad (134) of the first device layer are formed of the same material (copper) to form a single body or structure (metal to metal bonding).
With respect to Claim 3, Min discloses (Fig 8-17) wherein the molding portion, and the pad of the device layers have surfaces, which are coplanar with each other, through the planarization process on the molding portion. (see Fig 14)
With respect to Claim 4, Yu teaches (Fig 14) wherein a via (136) of the second device layer is coupled to the second redistribution substrate.
With respect to Claim 5, Yu teaches (Fig 14) wherein the second redistribution substrate comprises an insulating pattern (182) and a conductive pattern (184) in the insulating pattern to be coupled to the second device layer.
With respect to Claim 6, Yu teaches (Fig 14) wherein a conductive pattern (184) of the second redistribution substrate comprises a wiring pattern and a via pattern forming a single body or structure having a character “T” shape, and wherein the wiring pattern and the via pattern correspond to a horizontal stroke and a vertical stroke of the character “T” shape, respectively.
With respect to Claim 7, Yu teaches (Fig 14) wherein a bottom surface of the molding portion (140b) and a bottom surface of a pad (134) of the second device layer are coplanar with each other, and wherein the pad of the second device layer is in contact with the via of the first device layer.
With respect to Claim 8, Yu teaches (Fig 14) wherein, at an interface of the first device layer and the second device layer, the pad of the second device layer and the via of the first device layer are formed of the same material (copper) to form a single body or structure (par 75)
With respect to Claim 9, Yu teaches (Fig 14) wherein an interface of the pad of the second device layer and the via of the first device layer and an interface of the molding portion of the first device layer and the molding portion of the second device layer are coplanar with each other.
With respect to Claim 11, Yu teaches (Fig 31), an embodiment comprising further comprising, before stacking the second device layer (130C) on the first device layer (130A), stacking a third device layer (130B) of the device layers on the first device layer, wherein the second device layer is stacked on the third device layer.
With respect to Claim 12, Yu teaches (Fig 31), an embodiment wherein the pad of the third device layer is in contact with the via of the first device layer, the molding portion of the third device layer is in contact with the molding portion of the first device layer, and wherein the pad of the second device layer is in contact with the via of the third device layer, the molding portion of the second device layer is in contact with the molding portion of the third device layer.
With respect to Claim 13, Yu teaches (Fig 14) further comprising forming outer terminals (190) on a top surface of the second redistribution substrate.
With respect to Claim 14, Min discloses (Fig 8-17) most aspects of the current invention including a method of manufacturing a semiconductor package, comprising:
forming a first device layer (3) that comprises a first die (3), a first pad (38) on the first die, and a first molding portion (5) surrounding the first die, the first molding portion at least partially covering an active surface of the first die and surrounding the first pad on the active surface of the first die, the first die comprises a first via (35) penetrating the first die and being exposed near an inactive surface of the first die
forming a second device layer (6) that comprises a second die (6), a second pad (16) on the second die and a second molding portion (7) surrounding the second die, the second molding portion at least partially covering an active surface of the second die and surrounding the second pad on the active surface of the second die,
bonding the first device layer to a first redistribution substrate (2) such that the first pad is coupled to the first redistribution substrate
stacking the second device layer on the first device layer
However, Min does not disclose the second die comprising a second via penetrating the second die and being exposed near an inactive surface of the second die, forming a penetration electrode to penetrate the first and second molding portions in a region around the first and second dies and to be coupled to the first redistribution substrate, forming a second redistribution substrate on the second device layer, wherein the second pad of the second device layer is between the first die of the first device layer and the second die of the second device layer, and wherein, at an interface of the first device layer and the second device layer, the first via of the first device layer and the second pad of the second device layer are formed of the same material to form a single body or structure.
On the other hand, and in the same field of endeavor, Yu teaches (Fig 1-10,14) a method of manufacturing a semiconductor package, comprising forming a first device layer (130A) that comprises a first die (130A), a first pad (134 of 130A) on the first die, and a first via (136) penetrating the first die and being exposed near an inactive surface of the first die, forming a second device layer (130B) that comprises a second die (130B), a second pad (134 of 130B) on the second die, and the second die comprising a second via (136) penetrating the second die and being exposed near an inactive surface of the second die, bonding the first device layer to a first redistribution substrate (220) such that the first pad is coupled to the first redistribution substrate, stacking the second device layer on the first device layer, forming a penetration electrode (120) to penetrate the first (first molding 140A) and second molding (second molding 140B) portions in a region around the first and second dies and to be coupled to the first redistribution substrate, forming a second redistribution substrate (170/180) on the second device layer, wherein the second pad (134 of 130B) of the second device layer is between the first die of the first device layer and the second die of the second device layer, and wherein, at an interface of the first device layer and the second device layer, the first via (136) of the first device layer and the second pad of the second device layer are formed of the same material (copper) to form a single body or structure (layers 136 of 130A, 154, 134 of 130B are all copper for direct metal to metal bonding). Yu teaches the penetration electrode are used to provide electrical connection between the first redistribution substrate and the second redistribution substrate and further to allow direct metal-to-metal bonding to be achieved even if misalignment occurs, thereby ensuring the reliability of electrical connections between the integrated circuit components.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have method steps of the second die comprising a second via penetrating the second die and being exposed near an inactive surface of the second die, forming a penetration electrode to penetrate the first and second molding portions in a region around the first and second dies and to be coupled to the first redistribution substrate, forming a second redistribution substrate on the second device layer, wherein the second pad of the second device layer is between the first die of the first device layer and the second die of the second device layer, and wherein, at an interface of the first device layer and the second device layer, the first via of the first device layer and the second pad of the second device layer are formed of the same material to form a single body or structure in the method of Min, as taught by Yu because the penetration electrode are used to provide electrical connection between the first redistribution substrate and the second redistribution substrate and further to allow direct metal-to-metal bonding to be achieved even if misalignment occurs, thereby ensuring the reliability of electrical connections between the integrated circuit components.
With respect to Claim 15, Yu teaches (Fig 14) wherein the first pad (134 of 130A) of the first device layer is between the first die of the first device layer and the first redistribution substrate, wherein the first redistribution substrate comprises an insulating pattern (250) and a conductive pattern (see metal 240) in the insulating pattern to be in contact with the first pad of the first device layer.
With respect to Claim 16, Yu teaches (Fig 14) wherein, at an interface of the first redistribution substrate and the first device layer, the conductive pattern (see metal 240) of the first redistribution substrate and the first pad (134 of 130A) of the first device layer are formed of the same material (copper) to form a single body or structure (metal to metal bonding).
With respect to Claim 17, Min discloses (Fig 8-17) wherein forming the first device layer comprises:
forming the first die (3), which comprises a first base layer (30), a first circuit layer (36) on the base layer, and the first via (35) provided to penetrate the first base layer and coupled to the first circuit layer; (Fig 10)
forming the first pad (38) on the first circuit layer of the first die, the first pad being coupled to the circuit layer; (Fig 10)
placing the first die on a first carrier substrate (82) such that the first base layer faces the first carrier substrate; (Fig 10)
coating the first carrier substrate with a molding material to form the first molding material (5) encapsulating the first die; (Fig 13)
performing a first planarization process on the first molding portion to expose the first pad; (Fig 14)
removing the first carrier substrate to expose the first base layer; (method step carried out in Fig 12)
Furthermore, although Min discloses wherein the second device layer is stacked on the first device layer, Min does not disclose wherein forming the second device layer comprises: forming the second die, which comprises a second base layer, a second circuit layer on the second base layer, and the second via provided to penetrate the second base layer and coupled to the second circuit layer; forming the second pad on the second circuit layer of the second die, the second pad being coupled to the second circuit layer; placing the second die on a second carrier substrate such that the second base layer faces the second carrier substrate; coating the second carrier substrate with a molding material to form the second molding portion encapsulating the second die; performing a second planarization process on the second molding portion to expose the second pad; and removing the second carrier substrate to expose the second base layer.
However, the courts have held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced: forming the second device layer as claimed by the applicant is therefore only considered to be a duplication of the device layer disclosed by Min that a person having ordinary skill in the routing art would have been able to implement in the design of the semiconductor package using routine layout techniques based, among other things, number of device layers, device layer dimensions, semiconductor package size, etc. (see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) )), since neither non-obvious nor unexpected results, i.e., results which are different in kind from the results of the prior art, will be obtained as long as the method of forming the first device layer is utilized to stack a plurality of device layers, as already suggested by Min.
Additionally, and, and in the same field of endeavor, Yu teaches (Fig 1-10,14) a method of manufacturing a semiconductor package, comprising forming a first device layer (130A) that comprises a first die (130A), a first pad (134 of 130A) on the first die, and a first via (136) penetrating the first die and being exposed near an inactive surface of the first die, forming a second device layer (130B) that comprises a second die (130B), a second pad (134 of 130B) on the second die, and the second die comprising a second via (136) penetrating the second die and being exposed near an inactive surface of the second die and stacking the second device layer on the first device layer, wherein the method for forming the first device layer and the second device layer are the same.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have forming the second device layer as claimed by the applicant, in the method of Min, as taught by Yu because it is known in the semiconductor packaging art to form device layers using a similar method, as taught by Yu, and applying a known method step for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to Claim 18, Yu teaches (Fig 14), wherein the first molding portion (first molding 140A) and the first pad of the first device layers have surfaces, which are coplanar with each other, through the first planarization process on the first molding portion, and wherein the second molding portion (second molding 140B) and the second pad of the second device layers have surfaces, which are coplanar with each other, through the second planarization process on the second molding portion.
With respect to Claim 19, Yu teaches (Fig 14), wherein the second via (136) of the second device layer is coupled to the second redistribution substrate (170/180).
With respect to Claim 20, Yu teaches (Fig 14), wherein an interface of the second pad of the second device layer and the first via of the first device layer and an interface of the first molding portion of the first device layer and the second molding portion of the second device layer are coplanar with each other.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Min (US 2020/0294964) in view of Yu (US 2021/0098381) and in further view of Hsu (US 2019/0006315).
With respect to Claim 10, Min in view of Yu shows most aspects of the present invention. However, the combination of references does not show wherein a thickness of the pad of the device layers ranges from 0.1 mm to 10 mm.
On the other hand, and in the same field of endeavor, Hsu teaches (Fig 1-2) a method of manufacturing a semiconductor package, comprising forming device layers that comprises forming a die (130), which comprises a base layer (131), a circuit layer (132) on the base layer, and a via (137) provided to penetrate the base layer and coupled to the circuit layer, forming a pad (134) on the circuit layer of the die, the pad being coupled to the circuit layer, wherein a thickness of the pad of the device layers ranges from 3 µm to 10 µm (0.003 mm to 0.01 mm) or 30 µm to 100 µm (0.03 mm to 0.1 mm).
However, it is noted that the specification fails to provide teachings about the criticality of having a thickness of the pad of the device layers which ranges from 0.1 mm to 10 mm.
Regarding claim 10, the courts have held that differences in the thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the thicknesses and similar thicknesses are known in the art (see e.g. Hsu), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Min in view of Yu.
Criticality: The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUINTON A BRASFIELD whose telephone number is (571)272-0804. The examiner can normally be reached M-F 9AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Q. B./
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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