Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 17 is objected to because of the following informalities: comprises should be corrected to comprise, as the subject of the clause, each of the one or more second dielectric layers and each of the one or more fourth dielectric layers, is plural. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claimed limitation “the dielectric material” does not have antecedent basis. For purposes of examination, this will be assumed to be the same as “a same dielectric material” of claim 7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. US 20240128333.
Regarding claim 1, Xie discloses a chip, comprising:
a first epitaxial (epi) layer (first layer 36, in figure 16a on the right, is an epitaxial layer [0065]);
a second epi layer (second layer 36, in figure 16a on the left, is an epitaxial layer [0065]);
a gate between the first epi layer and the second epi layer (a gate comprises the middle elements 40L/42 described in [0072] located between the two epi layers labeled elements 36, where 40L is the lowest of the layers 40 that is closest to 42);
one or more channels coupled between the first epi layer and the second epi layer (semiconductor channel material nanosheets 20NS are located between the two epi layers labeled elements 36 [0074]),
wherein the one or more channels pass through the gate (see figure 16a and [0074]); and
a dielectric stack under the gate (a dielectric stack under the gate comprises elements 26/40/28/41 in figure 16a, rotated by 180 degrees [0074),
the dielectric stack including: one or more first dielectric layers (figure 16a, 26, 40); and
one or more second dielectric layers (figure 16a, 41, 28).
Regarding claim 2, Xie discloses the chip of claim 1, further comprising a backside contact coupled to a bottom surface of the first epi layer (figure 16a, rotated by 180 degrees, element 56 [0085]).
Regarding claim 3, Xie discloses the chip of claim 1, wherein the gate comprises a high-k (HK) dielectric material and a gate metal, and each of the one or more first dielectric layers comprises the HK dielectric material (paragraph [0074] discloses that gate, element 40L/42, figure 16a, comprises a high-k dielectric layer 40L and a metal layer 42).
Regarding claim 4, Xie discloses the chip of claim 3, wherein a thickness of each of the one or more first dielectric layers is equal to or less than twice a thickness of the HK dielectric material in the gate. Annotated figure 16A shows the horizontal thickness of two of the gate dielectric material layers. The horizontal thickness of each of the first dielectric layers 26 and 41 are evidently less than or equal to this indicated thickness.
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Regarding claim 5, Xie discloses the chip of claim 3, wherein the HK dielectric material comprises at least one of Hafnium Oxide (HfO2), Zirconium Oxide (ZrO₂), Aluminum Oxide (Al₂O₃), Tantalum Pentoxide (Ta₂O₅), Lanthanum Oxide, Titanium oxide (TiO2), Yttrium(III) Oxide (Y2O3), and Lanthanum Doped Zirconium Oxide (LaZrO2) (paragraph [0071] discloses that the high-k dielectric layer could comprise at least one of HfO2, lanthanum oxide, ZrO₂, Ta₂O₅, titanium oxide, Y2O3, and Al₂O₃, among other similar materials).
Regarding claim 6, Xie discloses the chip of claim 1, further comprising:
a first gate spacer (figure 16A, element 30 [0074]); and
a second gate spacer (figure 16A, element 30 [0074]),
wherein a portion of the gate is disposed between the first gate spacer and the second gate spacer (gate portion 42 is disposed between the two elements 30 in figure 16A).
Regarding claim 7, Xie discloses the chip of claim 6, wherein each of the one or more second dielectric layers comprises a same dielectric material as the first gate spacer and the second gate spacer (see paragraph [0059]).
Regarding claim 8, Xie discloses the chip of claim 7, wherein the dielectric material comprises at least one of silicon nitride (SiN), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and carbon-doped silicon oxide (SiCOH) (paragraph [0059] discloses that the dielectric material could comprise SiN or SiOCN).
Regarding claim 9, Xie discloses the chip of claim 1, wherein
the one or more first dielectric layers comprise two or more first dielectric layers (figure 16A shows that the first dielectric layers comprise first dielectric sublayers 26 and 40),
the one or more second dielectric layers comprise two or more second dielectric layers (figure 16A shows that the second dielectric layers comprise second dielectric sublayers 28 and 41), and
the dielectric stack alternates between the two or more first dielectric layers and the two or more second dielectric layers (see figure 16A – where two or more first dielectric sublayers 40 are stacked with two second dielectric sublayers 28 and 41).
Regarding claim 10, Xie discloses the chip of claim 1, wherein a width of the gate is approximately equal to a width of the dielectric stack (gate layers 42 and 40L, the lowest layer 40 in figure 16A, and dielectric layers 40 are almost exactly same width, while dielectric layers 26, 41, and 28 are approximately the same, being the width of the gate plus the width of the spacers 30).
Regarding claim 11, Xie discloses the chip of claim 1, further comprising a backside interlayer dielectric (BS-ILD) extending under the dielectric stack and the first epi layer (paragraph [0085] discloses that the backside interlayer dielectric 54 is comprised by multilayer backside interlayer dielectric layer 55 in figure 16A, which extends under the dielectric stack and the first epitaxial layer).
Regarding claim 12, Xie discloses the chip of claim 11, further comprising a backside contact extending through the BS-ILD, wherein the backside contact is coupled to a bottom surface of the first epi layer (paragraphs [0084 and 0085] disclose backside contact structure 56, that, as shown in figure 16a, extends through the BS-IDL multilayer 55).
Regarding claim 13, Xie discloses the chip of claim 12, further comprising a backside rail, wherein the backside contact is coupled between the bottom surface of the first epi layer and the backside rail (paragraph [0086] discloses backside power rail 58, wherein the backside contact 56 is coupled between the bottom surface of the first epi layer 36 and the backside power rail 58 – noting this is when figure 16a is rotated 180 degrees).
Regarding claim 14, Xie discloses a chip, comprising:
a first gate (a first gate comprises the right-most element 40L/42 described in [0072], where 40L is the lowest of the layers 40, closest to 42);
a second gate(a second gate comprises the middle element 40L/42 described in [0072], where 40L is the lowest of the layers 40, closest to 42);
an epitaxial (epi) layer between the first gate and the second gate (first layer 36, in figure 16a on the right, is an epitaxial layer [0065] that is located between the first gate and the second gate);
a first dielectric stack under the first gate (the dielectric stack under the first gate comprises elements 26/40/28/41 in figure 16a [0074]),
the first dielectric stack including: one or more first dielectric layers (figure 16a, 26, 40); and
one or more second dielectric layers (figure 16a, 26, 40);
a second dielectric stack under the second gate (the dielectric stack under the second gate comprises elements 26/40/28/41 in figure 16a [0074]),
the second dielectric stack including: one or more third dielectric layers (figure 16a, 26, 40);
and one or more fourth dielectric layers (figure 16a, 26, 40); and
a backside contact extending between the first dielectric stack and the second dielectric stack (figure 16a, element 56 [0085]),
wherein the backside contact is coupled to a bottom surface of the first epi layer (the backside contact, 56, is coupled to the first epitaxial layer 36 [0086], where figure 16a is rotated by 180 degrees) .
Regarding claim 15, Xie discloses the chip of claim 14,
wherein each of the first gate and the second gate comprises a high-k (HK) dielectric material and a gate metal, and
each of the one or more first dielectric layers and each of the one or more third dielectric layers comprises the HK dielectric material.
Regarding claim 16, Xie discloses the chip of claim 14, further comprising:
a first gate spacer (figure 16A, element 30 [0074]); and
a second gate spacer (figure 16A, element 30 [0074]),
wherein a portion of the first gate is disposed between the first gate spacer and the second gate spacer (gate portion 42 is disposed between the two elements 30 in figure 16A).
Regarding claim 17, Xie discloses the chip of claim 16, wherein each of the one or more second dielectric layers and each of the one or more fourth dielectric layers comprises a same dielectric material as the first gate spacer and the second gate spacer (see paragraph [0059]).
Regarding claim 18, Xie discloses the chip of claim 14, wherein a width of the first gate is approximately equal to a width of the first dielectric stack, and a width of the second gate is approximately equal to a width of the second dielectric stack (first gate layers 42 and 40L, the lowest layer 40 in figure 16A, and dielectric layers 40 of the first dielectric stack are almost exactly same width, while dielectric layers 26, 41, and 28 of the first dielectric stack are approximately the same, being the width of the first gate plus the width of the spacers 30).
Regarding claim 19, Xie discloses the chip of claim 14,
wherein the one or more first dielectric layers comprise two or more first dielectric layers (figure 16A shows that the first dielectric layers comprise first dielectric sublayers 26 and 40),
the one or more second dielectric layers comprise two or more second dielectric layers (figure 16A shows that the second dielectric layers comprise second dielectric sublayers 28 and 41), and
the first dielectric stack alternates between the two or more first dielectric layers and the two or more second dielectric layers (see figure 16A – where two or more first dielectric sublayers 40 are stacked with two second dielectric sublayers 28 and 41 in the first dielectric stack).
Regarding claim 20, Xie discloses the chip of claim 19,
wherein the one or more third dielectric layers comprise two or more third dielectric layers (figure 16A shows that the third dielectric layers comprise third dielectric sublayers 26 and 40),
the one or more fourth dielectric layers comprise two or more fourth dielectric layers (figure 16A shows that the fourth dielectric layers comprise second dielectric sublayers 28 and 41), and
the second dielectric stack alternates between the two or more third dielectric layers and the two or more fourth dielectric layers (see figure 16A – where two or more third dielectric sublayers 40 are stacked with two fourth dielectric sublayers 28 and 41 in the second dielectric stack).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Li et al. US 20240113193 discloses a similar chip with epitaxial layers, dielectric stacks and backside contact. Johnson et al. US 20250294847 discloses methods of direct backside contact integration. Kang et al. US 20250169168 discloses a similar microelectronic structure with backside contact.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATRINA WALJESKI-MOSES/ Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
