DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 9-16, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8, 17, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (PGPUB 20090089492), hereinafter as Yoon.
Regarding claim 1, Yoon teaches a semiconductor memory device comprising: a first plane including a first memory cell array a second plane including a second memory cell array (Fig. 1, shows a memory plane/array with a plurality of sub-plane/sub-array partitions); and
a control circuit configured to: receive a first command set related to the first plane, output a first signal indicating whether or not the first plane is ready for a read operation in a first time period of executing a first operation on the first plane in response to the first command set ([0072] “during which write or erase operations are in process… use the read/busy output signal "R/B_" to detect whether the flash memory device is in a ready condition…ready to be read”), output a second signal indicating whether or not the first plane is ready for an operation in the first time period (“ready condition”, and mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.), and output a ready/busy signal indicating whether or not the semiconductor memory device is ready for the operation in the first time period ([0072-3]).
Regarding claim 2, Yoon teaches receive a second command set related to status information, and output the first signal, the second signal and a third signal in response to the second command set ([0072-73], and case law used in rejection of claim 1 applies for more signals to be generated).
Regarding claim 3, Yoon teaches the operation is a write operation, a read operation or an erase operation ([0072-73] write or erase operation in process).
Regarding claim 4, Yoon teaches the second signal indicates a ready state, while the ready/busy signal indicates the ready state ([0072-73] “ready condition”).
Regarding claim 5, Yoon teaches the second signal indicates a busy state, while the ready/busy signal indicates the busy state ([0072-73] whether “ready”).
Regarding claim 6, Yoon teaches the second signal indicates a ready state, while the ready/busy signal indicates a busy state ([0072-73] and case law used in rejection of claim 1 applies for a second “ready signal”).
Regarding claim 8, Yoon teaches the control circuit is further configured to output a third signal indicating pass or fail of the operation, when the second signal indicates a ready state ([0073] to detect ready/busy immediately after operations are finished).
Regarding claim 17, Yoon teaches output the second signal indicating that the first plane is ready for the operation set up to the receipt of the first command set ([0072-73], Note: “ready for the operation set up to the receipt” is interpreted as “ready to receive”).
Regarding claim 19, Yoon teaches the first operation includes a write operation, and the control circuit is configured to execute the write operation on the first memory cell array in response to the first command set ([0073]).
Regarding claim 20, Yoon teaches the first operation includes an erase operation, and the control circuit is configured to execute the erase operation on the first memory cell array in response to the first command set ([0073]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoon, in view of Tokiwa (PGPUB 20100277968), hereinafter as Tokiwa.
Regarding claim 7, Yoon teaches a circuit as of claim 1,
But not expressly a signal indicates a ready state, while the ready/busy signal indicates a busy state when the first time period is overlapped with a second time period of executing a second operation on the second plane in response to a third command set.
Tokiwa teaches a signal indicates a ready state, while the ready/busy signal indicates a busy state when the first time period is overlapped with a second time period of executing a second operation on the second plane in response to a third command set ([0116]).
Since Yoon and Tokiwa are both from the same field of semiconductor memory device, the purpose disclosed by Tokiwa would have been recognized in the pertinent art of Yoon.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to output a busy signal as in Tokiwa into the device of Yoon for the purpose of managing the operation of the memory device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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/MIN HUANG/Primary Examiner, Art Unit 2827