DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, claim 1 recites “at least one transistor comprising at least two channels” in line 2, which creates a lack of clarity as to whether each transistor comprises at least two channels or if the transistors collectively comprise at least two channels.
Further, claim 1 recites “the basis of a semiconductor material” in line 3 of the first limitation and in lines 1-2 of the eleventh limitation, which creates a lack of clarity as to what is meant by ‘the basis’ with regard to a semiconductor material. Perhaps this is a translation error from the original French application, but it creates a lack of clarity in the scope of claim 1. Additionally, reciting this phrase twice creates an additional lack of clarity as to which ‘semiconductor material’ is being referred to. Similarly, lines 4 and 6-7 of the eleventh limitation each recite “the basis of the semiconductor material” which create a lack of clarity for similar reasons. Moreover, claim 7 similarly recites “the basis of a semiconductor oxide” and should be remedied accordingly.
Further, throughout claim 1, the channels recited are introduced as “at least two channels” and then referred to “said channels” (lines 3-4 of claim 1), “each channel” (line 4 of the second limitation), “channels” (line 4 of the eleventh limitation), “the semiconductor material-based channels” (line 3 of the thirteenth limitation), and “the channels” (line 2 of the last limitation) which collectively creates a lack of clarity as to which channels are being referred to in each instance. In order to prevent creating such a lack of clarity, it is generally advisable to refer to ‘at least two channels’ as “the at least two channels” or “each of the at least two channels” consistently throughout the claim set.
Finally, line 4 of the first limitation and line 6 of the eleventh limitation each recite “a source and a drain” which creates a lack of clarity as to which source and drain are being referred to.
Claims 2-15 include all the limitations of claim 1, therefore, are rejected for the same reasons presented above.
While claims 1-15 have been examined for further lack of clarity issues, it is advised that Applicant review the claim set for further clarity issues to ensure that the claim language as presented (and translated from the original French) accurately reflects Applicant’s desired claim scope.
The claim analysis that follows is presented as the claim set is best understood given the lack of clarity therein and may change depending upon any amendments made in overcoming the 35 U.S.C. 112(b) rejections of the claim set.
Allowable Subject Matter
Claims 1-15, as best understood, appear to be allowable subject matter. Specifically, claim 1, as best understood and in its current form, recites “removing totally, from the third openings, the first material of the remaining parts of the first layers, so as to form third spaces surrounding the semiconductor material-based channels” which is not disclosed in the prior art uncovered. Further, while the majority of limitations are fully disclosed and certain other limitations are generally disclosed, these other limitations are not disclosed in the claimed order and, on occasion, with the claimed alignment.
For instance, US 2021/0135015 A1 to Frougier (hereinafter “Frougier”) discloses providing a layer stack 15 on substrate 11 of alternating Si nanosheet channel layers 10 and SiGe sacrificial layers 12 with an additional sacrificial layer 14; patterning the stack 15 into fins 18 with associated openings; sacrificial gate structures 22 formed which overlap portions of the fins 18; sidewall spacers 26 formed adjacent to the sidewalls of the sacrificial gate structures 22; recesses 25 formed in the fins 18 which are self-aligned by spacers and gates; sacrificial layers 12 are recessed and inner spacers 30 formed by conformal dielectric fill of the recesses with an anisotropic etch; fully removing the initial nanosheet channel layers 10 selectively to form spaces 32 that extend across the width after inner spacers; gate dielectric of the final gate structures is formed, in part, in spaces; a 2D material conformally deposited that partially fills the spaces 32 with replacement channel layers 34 which forms layer 36 wrapping spacers and creates the 2D channels after selective removal of initial layers with source/drain connections via the 2D material layer 36; a replacement gate process where sacrificial gates are removed to allow final gate formation; spaces created around the 2D channels for gate wrap-around; gate electrodes formed with sections that wrap about the channel regions of the 2D layers in a gate-all-around arrangement.
Moreover, US 2023/0008409 A1 to Chou et al. (hereinafter “Chou”) comes closest in disclosing what Frougier does not by disclosing GAA FETs using 2D semiconductor nanosheets as channels, formation of a dummy/sacrificial gate, sidewall spacers, selective removal of sacrificial semiconductor nanosheets after dummy gate processing to create spaces between the 2D channels, formation of inner spacers, deposition of gate dielectric into the resulting spaces/trenches that surround the 2D channels, and final replacement-gate fill that fully surrounds the 2D channels, where the 2D material is integrated into a stacked nanosheet-like structure with channel-release after dummy-gate/spacer steps, and source/drain regions being engineered in relation to the 2D layers.
Further, US 2023/0170396 A1 to Frougier et al. (hereinafter “Frougier ‘396”) discloses a full process sequence built around an initial alternating stack with first and second materials different from the final channel semiconductor, patterning into openings/patterns, a sacrificial/dummy gate mounted on and partially in the openings, first sidewall spacers, second openings, internal/inner spacers, selective total removal of one set of layers to create spaces that expose parts of the sacrificial gate, deposition of a gate dielectric into those spaces on exposed sacrificial-gate portions and remaining layers and aligned with the sacrificial gate, deposition of the 2D semiconductor material on that dielectric aligned with both the sacrificial gate and first spacers so that it forms both the stacked channels and the source/drain, subsequent sacrificial-gate removal, total removal of the remaining alternating-layer material to create fully surrounding spaces around the channels, and fill with gate material to produce a GAA. However, none of the references cited nor any other uncovered, appear to disclose removing totally, from the third openings, the first material of the remaining parts of the first layers, so as to form third spaces surrounding the semiconductor material-based channels, in addition to the particular sequence claimed in claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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