Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/27/2026 has been entered.
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 07/28/2026. The changes and remarks disclosed therein have been considered. Claims 2-3, 11- 12 and 20-21 have been cancelled by the amendment. Claims 1, 10 and 19 have been amended. Therefore, claims 1, 4-10, 13-19, 22-27 remain pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 13, 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 4, 13, 22 recite “the status read operation”. There is insufficient antecedent basis for this limitation in the claims, as this is the first recitation. For the purpose of examination, it is assumed that "the status read operation" is instead "a status read operation".
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-10, 13-19, 22-27 are rejected under 35 U.S.C. 103 as being unpatentable over Darragh PG PUB 20160180959 (hereinafter Darragh), in view of Zainuddin PG PUB 20240395343 (hereinafter Zainuddin).
Regarding independent claim 1, Darragh teaches a wear leveling method (“wear leveling” is interpreted broadly, depend claim 5 explicitly recites determining wear leveling based on program/erase cycle counts. Accordingly, claim 1 reasonably encompass any block-management operation performed based on a wear indicator, including but not limit to P/E count, error count, failed-bit count, or block health metrics, therefore, operations such as including degrading blocks, migrating data, and shifting usage to other blocks constitute wear leveling) for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising a plurality of physical erasing units (“block” indicated in title and abstract of Darragh), the wear leveling method comprising:
an error detecting and correcting operation is not performed during a process of obtaining the open bit count (Darragh teaches obtaining an open bit count, broadly interpreted as a count or metric indicative of bit failure, weak bits, or degradation of memory cells, for each block ([0151-152]). Darragh teaches measuring failed bit count (FBC) based on read operations ([0151]-[0152], while ECC processing is separated disclosed ([0150], [0161]). Darragh does not require ECC correction to be performed during process of obtaining the FBC. Rather, Darragh indicated the ECC processing may be applied after data is obtained (e.g., “errors from read disturb may be removed by processing the decoded data post-ECC correction” in [0161]), demonstrating that error measurement and ECC correction are distinct operations, accordingly, It would have been obvious to a person of ordinary skill in the art to perform the error measurement without ECC correction during the counting process because ECC correction alters raw error information and may mask underlying error characteristics, whereas measurement on uncorrected data provided a more accurate indication of memory degradation for wear-leveling decisions);
determining whether there is a first physical erasing unit with the open bit count greater than a first threshold (Darragh teaches threshold-based identification of blocks using error metrics, [0125] of Darragh, “…detected blocks may then be mapped out as bad if they are below a threshold…”, [0128] of Darragh, “…high level of wear may be a threshold above which the memory is not designed to operate properly…”); and
in response to there being the first physical erasing unit with the open bit count greater than the first threshold, performing a first wear leveling operation (“wear leveling operation” has been interpreted as any management operation that redistributes usage of blocks based on their wear condition, including block selection, avoidance, replacement, or reassignment, “first wear leveling” has been interpreted as block cycling) on the first physical erasing unit (Darragh teaches wear leveling based on block-level wear/error metrics, [0119] of Darragh, “…memory block cycling may be a wear leveling method based on the EOL prediction described above...”, [0114] of Darragh, “… blocks are cycled in an attempt to level the wear remaining for each block…”, [0177] of Darragh, “…Wear leveling can be used so that the BER slope for each block is extended towards the same end of life point…”)
But Darragh does not teach applying the read voltage to programmed memory cells to obtain a count defined by memory cell having a threshold voltage greater than the read voltage.
Zainuddin teaches applying reference/read voltages to programmed memory cells to determine whether the threshold voltage of a memory cell is above or below the applied reference voltage ([0129]-[0130]). Zainuddin further teaches obtaining a bitscan count corresponding to a count of memory cells whose threshold voltages exceed a selected voltage level ([108], figure 9A-9B, [0111]-[0112]).
Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date to employ Zainuddin’s threshold-voltage sensing and bitscan-counting technique in Darragh’s FBC/error measurement process because both references evaluate the condition of programmed cells by determining cell populations relative to threshold/reference voltage. Doing so would have provided Darragh with a known quantitatively technique for determining the number of memory cells exhibiting a selected threshold-voltage condition, thereby facilitating block-level degradation and wear assessment.
Regarding claim 4, the combination of Darragh and Zainuddin teaches the wear leveling method according to claim 2, wherein the error detecting and correcting operation is not performed during a process of performing the status read operation ([0150] of Darragh, “…Other methods may reduce the amount of histogram analysis by substituting inferred data from what is happening to the error rate under certain conditions…” [0161] of Darragh, “…errors from read disturb may be removed by processing the decoded data post-ECC correction such that the errors that were due to Er to A state flips, for example, can be removed from the FBC analysis…”, these passages demonstrate that Darragh contemplates measuring failed bits without relying on ECC correction during read operation).
Regarding claim 5, the combination of Darragh and Zainuddin teaches the wear leveling method according to claim 1, further comprising: obtaining an average program/erase count of the physical erasing units; determining whether the average program/erase count is greater than a switching threshold; and in response to the average program/erase count not being greater than the switching threshold, performing a second wear leveling operation based on a program/erase count of each of the physical erasing units (Darragh teaches tracking wear in relation to P/E cycles, [0164] of Darragh, “… function of how wear FBC, or the overlap area, grows with more Program/Erase (P/E) cycles…” [0160] of Darragh, “…the process may include: … update …the block's maximum P/E value for wear leveling…” thus Darragh teaches obtaining P/E cycle information for blocks and using it in wear level operation).
Regarding claim 6, the combination of Darragh and Zainuddin teaches the wear leveling method according to claim 5, further comprising: in response to the average program/erase count being greater than the switching threshold, performing the first wear leveling operation based on the open bit count of each of the physical erasing units (Darragh teaches that wear increases with P/E cycling ([0164]) and that a threshold level of wear exists above which the memory is not designed to operate properly ([0128]). Darragh further teaches triggering changes in operation, including block cycling and wear leveling, in response to blocks exceeding such wear thresholds ([0114] of Darragh, [0119] of Darragh). Because wear in Darragh is driven by P/E cycling, comparing wear to a threshold inherently corresponds to determining whether a P/E related wear metric exceeds a switching threshold).
Regarding claim 7, the combination of Darragh and Zainuddin teaches the wear leveling method according to claim 5, further comprising: in response to the average program/erase count being greater than the switching threshold, performing the first wear leveling operation based on the program/erase count of each of the physical erasing units and the open bit count of each of the physical erasing units (Darragh teaches combining error-based wear metrics with P/E cycle information, [0160] of Darragh, “…the process may include: … estimate the current BER … update the block's maximum P/E value for wear leveling…”)
Regarding claim 8, the combination of Darragh and Zainuddin teaches the wear leveling method according to claim 1, wherein the open bit count is configured to indicate a degree of wear of each of the physical erasing units ([0115] of Darragh, “…actual wear may be the error rate or bit error rate…” [0149] of Darragh, “…Wear can be identified and measured …contribute to read errors…”)
Regarding claim 9, the combination of Darragh and Zainuddin teaches the wear leveling method according to claim 1, further comprising: in response to a number of the physical erasing units with the open bit count exceeding a warning threshold being greater than a threshold, outputting a warning signal ([0128] of Darragh, “…high level of wear may be a threshold above which the memory is not designed to operate properly…” [0125] of Darragh, “…detected blocks may then be mapped out as bad…”, providing indication/warning when the number of degraded blocks exceed limit would have been an obvious system-health notification).
Regarding claim 10, is substantially the apparatus counterpart of claim 1, thus is rejected over Darragh in view of Zainuddin.
Regarding claim 13, the combination of Darragh and Zainuddin teaches the memory storage device according to claim 11, wherein the error detecting and correcting operation is not performed during a process of the memory control circuit unit performing the status reading operation ([0150] of Darragh, “…Other methods may reduce the amount of histogram analysis by substituting inferred data from what is happening to the error rate under certain conditions…” [0161] of Darragh, “…errors from read disturb may be removed by processing the decoded data post-ECC correction such that the errors that were due to Er to A state flips, for example, can be removed from the FBC analysis…”, these passages demonstrate that Darragh contemplates measuring failed bits without relying on ECC correction during read operation).
Claim 14 is rejected for the same reason set forth above with respect to claim 5.
Claim 15 is rejected for the same reason set forth above with respect to claim 6.
Claim 16 is rejected for the same reason set forth above with respect to claim 7
Claim 17 is rejected for the same reason set forth above with respect to claim 8.
Claim 18 is rejected for the same reason set forth above with respect to claim 9.
Regarding independent claim 19, is essentially the controller counterpart of claims 1/10, thus is rejected over Darragh in view of Zainuddin, with Darragh supplying the controller architecture, FBC/error measurement, threshold determination and wear-leveling functionality, and Zainuddin supplying the newly recited read-voltage/Vt relationship and cell-counting technique.
Regarding claim 22, the combination of Darragh and Zainuddin teaches the memory control circuit unit according to claim 20, wherein the error detecting and correcting circuit does not perform the error detecting and correcting operation during a process of the memory management circuit performing the status read operation ([0150] of Darragh, “…Other methods may reduce the amount of histogram analysis by substituting inferred data from what is happening to the error rate under certain conditions…” [0161] of Darragh, “…errors from read disturb may be removed by processing the decoded data post-ECC correction such that the errors that were due to Er to A state flips, for example, can be removed from the FBC analysis…”, these passages demonstrate that Darragh contemplates measuring failed bits without relying on ECC correction during read operation).
Claim 23 is rejected for the same reason set forth above with respect to claim 5.
Claim 24 is rejected for the same reason set forth above with respect to claim 6.
Claim 25 is rejected for the same reason set forth above with respect to claim 7.
Claim 26 is rejected for the same reason set forth above with respect to claim 8.
Claim 27 is rejected for the same reason set forth above with respect to claim 9.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant argues that Darragh fails to teach or suggest the limitations of independent claim 1 requiring “applying a read voltage to a plurality of memory cells in each of the physical erasing units in a writing state to obtain an open bit count … wherein an open bit is stored in a memory cell having a threshold voltage greater than the read voltage,” and further requiring that “an error detecting and correcting operation is not performed during a process of obtaining the open bit count”.
Applicant first contends that Darragh’s failed-bit-count (FBC) determination necessarily relies upon execution of an ECC operation. The examiner respectfully disagrees. Darragh distinguishes the measurement of error information from subsequent processing of that information. For example, Darragh teaches determining an FBC/error-rate characteristic by performing read operations and counting cells associated with particular threshold-voltage states ([0151]-[0154]). Including processing of decoded data after ECC correction to remove particular error contributions ([0161] of Darragh). Thus the disclosure of ECC circuitry of ECC processing elsewhere in Darragh does not establish that ECC correction must be performed during the particular operation in which the failed-bit information is obtained.
More importantly, the rejection is under 35 U.S.C. 103. Even assuming that one implementation of Darragh employs ECC in connection with its error analysis, a person of ordinary skill in the art would have recognized that error information may be determined from the read results before correction when the purpose if to characterize the underlying condition of memory cells. Applying ECC correction before determining the raw error characteristic would alter the error information being measurement and may mask the very bit failures or threshold-voltage deviations being evaluated. Accordingly, it would have been an obvious implementation choice to obtain the relevant count from the read results without performing error correction during that counting operation, while permitting ECC processing to occur separately for other purposes. This is consistent with Darragh’s treatment of error measurement and ECC-related processing as distinguishable operations.
Applicant next argues that Darragh performs its counting during a “standard read operation”, whereas presently amended claim 1 requires applying the read voltage while the cells are “in a writing state”. This argument is not persuasive because the claimed phrase “in a writing state” does not require that a program pulse be applied simultaneously with the claimed read voltage. Applicant argument does not overcome the rejection because the rejection does not rely on Darragh alone for the newly added read-voltage limitation. Darragh provides the wear-leveling and error cauterization framework, while Zainuddin teaches applying reference/read voltages to programmed memory cells and determining cell population based on whether their threshold voltages are above or below the applied reference voltage.
Applicant further argues that Darragh’s FBC is merely an error-rate measurement for a codeword or page and differs from the claimed “open bit count”. This argument is not persuasive because the rejection does not rely solely on Darragh’s terminology. Claim 1 defines the relevant open bit functionality by the threshold-voltage relationship, a counted bit corresponding to a memory cell having a threshold voltage greater than the applied read voltage. Darragh determines cell populations from threshold voltage distributions using applied read thresholds and counts cells falling on one side those thresholds, while Zainuddin teaches determining cell populations based on whether the threshold voltages of programmed cells are above or below an applied reference/read voltage. Thus the combination provides the claimed functional relationship of counting memory cells satisfying the specified threshold-voltage condition. The particular terminology assigned to the resulting count does not distinguish the claimed operation from the combined teaching.
For at least the foregoing reasons, the Examiner maintains the position previously set forth.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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