Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 04/14/2026. The changes and remarks disclosed therein have been considered. Claims 1, 4, 10, 13, 19, 22 have been amended. Therefore, claims 1-27 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Darragh PG PUB 20160180959 (hereinafter Darragh).
Regarding independent claim 1, Darragh teaches a wear leveling method (“wear leveling” is interpreted broadly, depend claim 5 explicitly recites determining wear leveling based on program/erase cycle counts. Accordingly, claim 1 must encompass any block-management operation performed based on a wear indicator, including but not limit to P/E count, error count, failed-bit count, or block health metrics, therefore, operations such as including degrading blocks, migrating data, and shifting usage to other blocks constitute wear leveling) for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising a plurality of physical erasing units (“block” indicated in title and abstract), the wear leveling method comprising:
obtaining an open bit count (“open bit count” has been interpreted as any count or metric indicative of bit failures, weak bits, or degradation of memory cells) of each of the physical erasing units (Darragh teaches in [0151]-[0152] to measure failed bit count vias read operation, [0151], “…proposed failed bit count (“FBC”) or error rate method may be based on the error rate measurement, approximated by taking multiple reads and measuring the FBC and by using the optimal read thresholds…”, [0152], “…bad cells may be identified and counted…”);
an error detecting and correcting operation is not performed during a process of obtaining the open bit count (Darragh teaches measuring failed bit count (FBC) based on read operations ([0151]-[0152], which inherently involves observation error conditions in read data. While Darragh discloses that ECC processing may be performed in the system (e.g., [150], [0161]), such disclosure does not require ECC correction to be performed during process of obtaining the FBC. Rather, Darragh indicated the ECC processing may be applied after data is obtained (e.g., “errors from read disturb may be removed by processing the decoded data post-ECC correction” in [0161]), demonstrating that error measurement and ECC correction are distinct operations, accordingly, It would have been obvious to a person of ordinary skill in the art to perform the error measurement without ECC correction during the counting process because ECC correction alters raw error information and may mask underlying error characteristics, whereas measurement on uncorrected data provided a more accurate indication of memory degradation for wear-leveling decisions);
determining whether there is a first physical erasing unit with the open bit count greater than a first threshold (Darragh teaches threshold-based identification of blocks using error metrics, [0125], “…detected blocks may then be mapped out as bad if they are below a threshold…”, [0128], “…high level of wear may be a threshold above which the memory is not designed to operate properly…”); and
in response to there being the first physical erasing unit with the open bit count greater than the first threshold, performing a first wear leveling operation (“wear leveling operation” has been interpreted as any management operation that redistributes usage of blocks based on their wear condition, including block selection, avoidance, replacement, or reassignment, “first wear leveling” has been interpreted as block cycling) on the first physical erasing unit (Darragh teaches wear leveling based on block-level wear/error metrics, [0119], “…memory block cycling may be a wear leveling method based on the EOL prediction described above...”, [0114], “… blocks are cycled in an attempt to level the wear remaining for each block…”, [0177], “…Wear leveling can be used so that the BER slope for each block is extended towards the same end of life point…”)
Regarding claim 2, Darragh teaches the wear leveling method according to claim 1, wherein obtaining the open bit count of each of the physical erasing units comprises: performing a status read operation on each of the physical erasing units to obtain the open bit count ([0151], “…proposed failed bit count (“FBC”) or error rate method may be based on the error rate measurement, approximated by taking multiple reads and measuring the FBC and by using the optimal read thresholds…”)
Regarding claim 3, Darragh teaches the wear leveling method according to claim 2, wherein performing the status read operation further comprises: applying a read voltage to a plurality of memory cells in each of the physical erasing units in a writing state to obtain the open bit count (Darragh teaches applying read voltages to memory cells and counting cells detected in particular states during read operations, [0154], “…By counting the number of cells that were detected in the A-state but in fact were part of the erase state, the scale of the erase state distribution can be approximated…”)
Regarding claim 4, Darragh teaches the wear leveling method according to claim 2, wherein the error detecting and correcting operation is not performed during a process of performing the status read operation ([0150], “…Other methods may reduce the amount of histogram analysis by substituting inferred data from what is happening to the error rate under certain conditions…” [0161], “…errors from read disturb may be removed by processing the decoded data post-ECC correction such that the errors that were due to Er to A state flips, for example, can be removed from the FBC analysis…”, these passages demonstrate that Darragh contemplates measuring failed bits without relying on ECC correction during read operation)
Regarding claim 5, Darragh teaches the wear leveling method according to claim 1, further comprising: obtaining an average program/erase count of the physical erasing units; determining whether the average program/erase count is greater than a switching threshold; and in response to the average program/erase count not being greater than the switching threshold, performing a second wear leveling operation based on a program/erase count of each of the physical erasing units (Darragh teaches tracking wear in relation to P/E cycles, [0164], “… function of how wear FBC, or the overlap area, grows with more Program/Erase (P/E) cycles…” [0160], “…the process may include: … update …the block's maximum P/E value for wear leveling…” thus Darragh teaches obtaining P/E cycle information for blocks and using it in wear level operation).
Regarding claim 6, Darragh teaches the wear leveling method according to claim 5, further comprising: in response to the average program/erase count being greater than the switching threshold, performing the first wear leveling operation based on the open bit count of each of the physical erasing units (Darragh teaches that wear increases with P/E cycling ([0164]) and that a threshold level of wear exists above which the memory is not designed to operate properly ([0128]). Darragh further teaches triggering changes in operation, including block cycling and wear leveling, in response to blocks exceeding such wear thresholds ([0114], [0119]). Because wear in Darragh is driven by P/E cycling, comparing wear to a threshold inherently corresponds to determining whether a P/E related wear metric exceeds a switching threshold).
Regarding claim 7, Darragh teaches the wear leveling method according to claim 5, further comprising: in response to the average program/erase count being greater than the switching threshold, performing the first wear leveling operation based on the program/erase count of each of the physical erasing units and the open bit count of each of the physical erasing units (Darragh teaches combining error-based wear metrics with P/E cycle information, [0160], “…the process may include: … estimate the current BER … update the block's maximum P/E value for wear leveling…”)
Regarding claim 8, Darragh teaches the wear leveling method according to claim 1, wherein the open bit count is configured to indicate a degree of wear of each of the physical erasing units ([0115], “…actual wear may be the error rate or bit error rate…” [0149], “…Wear can be identified and measured …contribute to read errors…”)
Regarding claim 9, Darragh teaches the wear leveling method according to claim 1, further comprising: in response to a number of the physical erasing units with the open bit count exceeding a warning threshold being greater than a threshold, outputting a warning signal ([0128], “…high level of wear may be a threshold above which the memory is not designed to operate properly…” [0125], “…detected blocks may then be mapped out as bad…”, identifying blocks exceeding wear thresholds and marking them for system response inherently corresponds to generating a warning or indication).
Regarding independent claim 10, Darragh teaches a memory storage device, comprising: a connection interface unit (figure 1, 2, e.g., 216 in figure 2), configured to couple to a host system (figure 1, 2); a rewritable non-volatile memory module (116 in figure 1), wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units (“block” indicated in title and abstract); and a memory control circuit unit (118 in figure 2), coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to:
obtaining an open bit count (“open bit count” has been interpreted as any count or metric indicative of bit failures, weak bits, or degradation of memory cells) of each of the physical erasing units (Darragh teaches in [0151]-[0152] to measure failed bit count vias read operation, [0151], “…proposed failed bit count (“FBC”) or error rate method may be based on the error rate measurement, approximated by taking multiple reads and measuring the FBC and by using the optimal read thresholds…”, [0152], “…bad cells may be identified and counted…”);
an error detecting and correcting operation is not performed during a process of obtaining the open bit count (Darragh teaches measuring failed bit count (FBC) based on read operations ([0151]-[0152], which inherently involves observation error conditions in read data. While Darragh discloses that ECC processing may be performed in the system (e.g., [150], [0161]), such disclosure does not require ECC correction to be performed during process of obtaining the FBC. Rather, Darragh indicated the ECC processing may be applied after data is obtained (e.g., “errors from read disturb may be removed by processing the decoded data post-ECC correction” in [0161]), demonstrating that error measurement and ECC correction are distinct operations, accordingly, It would have been obvious to a person of ordinary skill in the art to perform the error measurement without ECC correction during the counting process because ECC correction alters raw error information and may mask underlying error characteristics, whereas measurement on uncorrected data provided a more accurate indication of memory degradation for wear-leveling decisions);
determining whether there is a first physical erasing unit with the open bit count greater than a first threshold (Darragh teaches threshold-based identification of blocks using error metrics, [0125], “…detected blocks may then be mapped out as bad if they are below a threshold…”, [0128], “…high level of wear may be a threshold above which the memory is not designed to operate properly…”); and
in response to there being the first physical erasing unit with the open bit count greater than the first threshold, performing a first wear leveling operation (“wear leveling operation” has been interpreted as any management operation that redistributes usage of blocks based on their wear condition, including block selection, avoidance, replacement, or reassignment, “first wear leveling” has been interpreted as block cycling) on the first physical erasing unit (Darragh teaches wear leveling based on block-level wear/error metrics, [0119], “…memory block cycling may be a wear leveling method based on the EOL prediction described above...”, [0114], “… blocks are cycled in an attempt to level the wear remaining for each block…”, [0177], “…Wear leveling can be used so that the BER slope for each block is extended towards the same end of life point…”)
Regarding claim 11, Darragh teaches the memory storage device according to claim 10, wherein the memory control circuit unit is further configured to: perform a status read operation on each of the physical erasing units to obtain the open bit count (Darragh teaches applying read voltages to memory cells and counting cells detected in particular states during read operations, [0154], “…By counting the number of cells that were detected in the A-state but in fact were part of the erase state, the scale of the erase state distribution can be approximated…”, [0151], “…proposed failed bit count (“FBC”) or error rate method may be based on the error rate measurement, approximated by taking multiple reads and measuring the FBC…”)
Regarding claim 12, Darragh teaches the memory storage device according to claim 11, wherein the memory control circuit unit is further configured to: apply a read voltage to a plurality of memory cells in each of the physical erasing units in a writing state to obtain the open bit count (Darragh teaches applying read voltages to memory cells and counting cells detected in particular states during read operations, [0154], “…By counting the number of cells that were detected in the A-state but in fact were part of the erase state, the scale of the erase state distribution can be approximated…”)
Regarding claim 13, Darragh teaches the memory storage device according to claim 11, wherein the error detecting and correcting operation is not performed during a process of the memory control circuit unit performing the status reading operation ([0150], “…Other methods may reduce the amount of histogram analysis by substituting inferred data from what is happening to the error rate under certain conditions…” [0161], “…errors from read disturb may be removed by processing the decoded data post-ECC correction such that the errors that were due to Er to A state flips, for example, can be removed from the FBC analysis…”, these passages demonstrate that Darragh contemplates measuring failed bits without relying on ECC correction during read operation).
Regarding claim 14, Darragh teaches the memory storage device according to claim 10, wherein the memory control circuit unit is further configured to: obtain an average program/erase count of the physical erasing units; determine whether the average program/erase count is greater than a switching threshold; and in response to the average program/erase count not being greater than the switching threshold, perform a second wear leveling operation based on a program/erase count of each of the physical erasing units (Darragh teaches tracking wear in relation to P/E cycles, [0164], “… function of how wear FBC, or the overlap area, grows with more Program/Erase (P/E) cycles…” [0160], “…the process may include: … update …the block's maximum P/E value for wear leveling…” thus Darragh teaches obtaining P/E cycle information for blocks and using it in wear level operation).
Regarding claim 15, Darragh teaches the memory storage device according to claim 14, wherein the memory control circuit unit is further configured to: in response to the average program/erase count being greater than the switching threshold, perform the first wear leveling operation based on the open bit count of each of the physical erasing units (Darragh teaches that wear increases with P/E cycling ([0164]) and that a threshold level of wear exists above which the memory is not designed to operate properly ([0128]). Darragh further teaches triggering changes in operation, including block cycling and wear leveling, in response to blocks exceeding such wear thresholds ([0114], [0119]). Because wear in Darragh is driven by P/E cycling, comparing wear to a threshold inherently corresponds to determining whether a P/E related wear metric exceeds a switching threshold).
Regarding claim 16, Darragh teaches the memory storage device according to claim 14, wherein the memory control circuit unit is further configured to: in response to the average program/erase count being greater than the switching threshold, perform the first wear leveling operation based on the program/erase count of each of the physical erasing units and the open bit count of each of the physical erasing units (Darragh teaches combining error-based wear metrics with P/E cycle information, [0160], “…the process may include: … estimate the current BER … update the block's maximum P/E value for wear leveling…”)
Regarding claim 17, Darragh teaches the memory storage device according to claim 10, wherein the open bit count is configured to indicate a degree of wear of each of the physical erasing units ([0115], “…actual wear may be the error rate or bit error rate…” [0149], “…Wear can be identified and measured …contribute to read errors…”)
Regarding claim 18, Darragh teaches the memory storage device according to claim 10, wherein the memory control circuit unit is further configured to: in response to a number of the physical erasing units with the open bit count exceeding a warning threshold being greater than a threshold, output a warning signal ([0128], “…high level of wear may be a threshold above which the memory is not designed to operate properly…” [0125], “…detected blocks may then be mapped out as bad…”, identifying blocks exceeding wear thresholds and marking them for system response inherently corresponds to generating a warning or indication).
Regarding independent claim 19, Darragh teaches a memory control circuit unit (118 in figure 2) for controlling a rewritable non-volatile memory module (116 in figure 1), wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units (“block” indicated in title and abstract), and the memory control circuit unit comprises:
a host interface (figure 1, 2, e.g., 216 in figure 2), configured to couple to a host system (100 in figure 1); a memory interface (204 in figure 2), configured to couple to the rewritable non-volatile memory module (116 in figure 1); an error detecting and correcting circuit (ECC 214 in figure 2); and a memory management circuit (206 in figure 2), coupled to the host interface (216 in figure 2), the memory interface (204 in figure 2), and the error detecting and correcting circuit (214 in figure 2), wherein the memory management circuit is configured to:
obtaining an open bit count (“open bit count” has been interpreted as any count or metric indicative of bit failures, weak bits, or degradation of memory cells) of each of the physical erasing units (Darragh teaches in [0151]-[0152] to measure failed bit count vias read operation, [0151], “…proposed failed bit count (“FBC”) or error rate method may be based on the error rate measurement, approximated by taking multiple reads and measuring the FBC and by using the optimal read thresholds…”, [0152], “…bad cells may be identified and counted…”);
an error detecting and correcting operation is not performed during a process of obtaining the open bit count (Darragh teaches measuring failed bit count (FBC) based on read operations ([0151]-[0152], which inherently involves observation error conditions in read data. While Darragh discloses that ECC processing may be performed in the system (e.g., [150], [0161]), such disclosure does not require ECC correction to be performed during process of obtaining the FBC. Rather, Darragh indicated the ECC processing may be applied after data is obtained (e.g., “errors from read disturb may be removed by processing the decoded data post-ECC correction” in [0161]), demonstrating that error measurement and ECC correction are distinct operations, accordingly, It would have been obvious to a person of ordinary skill in the art to perform the error measurement without ECC correction during the counting process because ECC correction alters raw error information and may mask underlying error characteristics, whereas measurement on uncorrected data provided a more accurate indication of memory degradation for wear-leveling decisions);
determining whether there is a first physical erasing unit with the open bit count greater than a first threshold (Darragh teaches threshold-based identification of blocks using error metrics, [0125], “…detected blocks may then be mapped out as bad if they are below a threshold…”, [0128], “…high level of wear may be a threshold above which the memory is not designed to operate properly…”); and
in response to there being the first physical erasing unit with the open bit count greater than the first threshold, performing a first wear leveling operation (“wear leveling operation” has been interpreted as any management operation that redistributes usage of blocks based on their wear condition, including block selection, avoidance, replacement, or reassignment, “first wear leveling” has been interpreted as block cycling) on the first physical erasing unit (Darragh teaches wear leveling based on block-level wear/error metrics, [0119], “…memory block cycling may be a wear leveling method based on the EOL prediction described above...”, [0114], “… blocks are cycled in an attempt to level the wear remaining for each block…”, [0177], “…Wear leveling can be used so that the BER slope for each block is extended towards the same end of life point…”)
Regarding claim 20, Darragh teaches the memory control circuit unit according to claim 19, wherein the memory management circuit is further configured to: perform a status read operation on each of the physical erasing units to obtain the open bit count ([0151], “…proposed failed bit count (“FBC”) or error rate method may be based on the error rate measurement, approximated by taking multiple reads and measuring the FBC and by using the optimal read thresholds…”)
Regarding claim 21, Darragh teaches the memory control circuit unit according to claim 20, wherein the memory management circuit is further configured to: apply a read voltage to a plurality of memory cells in each of the physical erasing units in a writing state to obtain the open bit count (Darragh teaches applying read voltages to memory cells and counting cells detected in particular states during read operations, [0154], “…By counting the number of cells that were detected in the A-state but in fact were part of the erase state, the scale of the erase state distribution can be approximated…”)
Regarding claim 22, Darragh teaches the memory control circuit unit according to claim 20, wherein the error detecting and correcting circuit does not perform the error detecting and correcting operation during a process of the memory management circuit performing the status read operation ([0150], “…Other methods may reduce the amount of histogram analysis by substituting inferred data from what is happening to the error rate under certain conditions…” [0161], “…errors from read disturb may be removed by processing the decoded data post-ECC correction such that the errors that were due to Er to A state flips, for example, can be removed from the FBC analysis…”, these passages demonstrate that Darragh contemplates measuring failed bits without relying on ECC correction during read operation).
Regarding claim 23, Darragh teaches the memory control circuit unit according to claim 19, wherein the memory management circuit is further configured to: obtain an average program/erase count of the physical erasing units; determine whether the average program/erase count is greater than a switching threshold; and in response to the average program/erase count not being greater than the switching threshold, perform a second wear leveling operation based on a program/erase count of each of the physical erasing units (Darragh teaches tracking wear in relation to P/E cycles, [0164], “… function of how wear FBC, or the overlap area, grows with more Program/Erase (P/E) cycles…” [0160], “…the process may include: … update …the block's maximum P/E value for wear leveling…” thus Darragh teaches obtaining P/E cycle information for blocks and using it in wear level operation).
Regarding claim 24, Darragh teaches the memory control circuit unit according to claim 23, wherein the memory management circuit is further configured to: in response to the average program/erase count being greater than the switching threshold, perform the first wear leveling operation based on the open bit count of each of the physical erasing units (Darragh teaches that wear increases with P/E cycling ([0164]) and that a threshold level of wear exists above which the memory is not designed to operate properly ([0128]). Darragh further teaches triggering changes in operation, including block cycling and wear leveling, in response to blocks exceeding such wear thresholds ([0114], [0119]). Because wear in Darragh is driven by P/E cycling, comparing wear to a threshold inherently corresponds to determining whether a P/E related wear metric exceeds a switching threshold).
Regarding claim 25, Darragh teaches the memory control circuit unit according to claim 23, wherein the memory management circuit is further configured to: in response to the average program/erase count being greater than the switching threshold, perform the first wear leveling operation based on the program/erase count of each of the physical erasing units and the open bit count of each of the physical erasing units (Darragh teaches combining error-based wear metrics with P/E cycle information, [0160], “…the process may include: … estimate the current BER … update the block's maximum P/E value for wear leveling…”)
Regarding claim 26, Darragh teaches the memory control circuit unit according to claim 19, wherein the open bit count is configured to indicate a degree of wear of each of the physical erasing units ([0115], “…actual wear may be the error rate or bit error rate…” [0149], “…Wear can be identified and measured …contribute to read errors…”)
Regarding claim 27, Darragh teaches the memory control circuit unit according to claim 19, wherein the memory management circuit is further configured to: in response to a number of the physical erasing units with the open bit count exceeding a warning threshold being greater than a threshold, output a warning signal ([0128], “…high level of wear may be a threshold above which the memory is not designed to operate properly…” [0125], “…detected blocks may then be mapped out as bad…”, identifying blocks exceeding wear thresholds and marking them for system response inherently corresponds to generating a warning or indication).
Response To Arguments
The Applicant' arguments (REMARKS, filed 04/14/2026) have been fully considered but they are not persuasive.
Applicant has amended the independent claims 1, 13, 19 with additional limitation(s): "an error detecting and correcting operation is not performed during a process of obtaining the open bit count", the Applicant argues that the prior arts of record do not specifically teach this limitation. In particular, applicant pointed out “referring to paragraphs [0150], [0151] and [0161] of Darragh, Darragh explicitly discloses using an ECC engine to correct data to obtain FBC/BER. The FBC obtained by Darragh through read operations generally needs to be decoded by the ECC engine. In other words, the method in Darragh is fundamentally dependent upon the ECC correction to determine error rates”.
Examiner respectfully disagrees.
First, Darragh teaches obtaining error metrics such as failed bit count (FBC) based on read operations. See Darragh [0151]-[0152] (“by taking multiple reads and measuring the FBC”). These teaching are directed to identifying and counting failed bits (i.e., error characteristics of memory cells) based on read results.
While Darragh also disclosed that ECC processing may be performed in the system (e.g., [0150], [0161]), such disclosure does not require ECC correction to be performed during the process of obtaining the FBC. Rather, Darragh explicitly indicates that ECC processing may be applied after data is obtained, for example to remove specific error sources such as read disturb ([0161]), accordingly, Darragh distinguishes between (1) error measurement (FBC analysis) and (2) subsequent ECC-based processing, demonstrating that these are separate operations.
Furthermore, Darragh’s analysis is based on tracking statistical behavior of error-related metrics over time, including failed bit count (FBC), bit error rate (BER), and distribution evolution over time across blocks as illustrated in Figures 23-33. In particular, Figure 33 illustrates convergence of block-level BER toward a maximum error rate at end of retention, which depends on accurate characterization of error distributions across memory blocks.
A person of ordinary skill in the art would recognize that such statistical characterization requires measurement of raw, uncorrected error data, because performing error detection and correction prior to measurement would remove and suppress bit errors, thereby distorting the measured FBC/BER values and preventing accurate modeling of distribution shape, spread, and convergence behavior. In particular, performing ECC during measurement would artificially reduce the observed BER and eliminate distribution tails, thereby defeating Darragh’s purpose of predicting end-of-life behavior.
Therefore, Darragh at least suggest, and inherently requires, obtaining error metrics without performing ECC correction during measurement process, while allowing ECC processing to be performed separately before or after measurement for other purposes.
Additionally, the claims do not exclude the presence of an ECC circuit in the system, but only required that ECC is not performed during the specific process of obtaining the open bit count, which is consistent with Darragh.
Accordingly, Darragh does not teach away from the claim limitation. Rather, It would have been obvious to a person of ordinary skill in the art to perform the error measurement without ECC correction during the counting process because ECC correction alters raw error information and may mask underlying error characteristics, whereas measurement on uncorrected data provided a more accurate indication of memory degradation for wear-leveling decisions.
For at least the foregoing reasons, the Examiner maintains the position previously set forth.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Primary Examiner, Art Unit 2824
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