DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 08/12/2024.
Claims 1-20 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 08/12/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Missing of Foreign Priority Document
3. A claim for foreign priority is acknowledged. However, papers required under 35 U.S.C. 119(a)-(d) have NOT been placed of record in the file.
Specification
4. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-2, and 16-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Reboh et al. (US 2025/0040240)
Regarding claim 1, Reboh discloses a semiconductor device comprising:
a substrate 1 (see Fig. 1, Fig. 4);
a wall structure 31 or 29 and 31 disposed on the substrate 1 and extending in a first direction (X-direction into the page of the drawing), wherein the wall structure includes a first side surface (left side surface) and a second side surface (right side surface) opposite to the first side surface in a second direction (Y-direction laterally to the sides of the page) intersecting the first direction;
a first lower active pattern 5 or 15 (fig. 4) disposed on the first side surface and including at least one first lower bridge pattern 5 spaced apart from the substrate 1;
a first upper active pattern 5 or 10 (fig. 4) disposed on the first side surface and including at least one first upper bridge pattern 5 spaced further apart from the substrate than the first lower active pattern;
a first gate structure 45 disposed on the first side surface and intersecting the first lower active pattern and the first upper active pattern;
a second lower active pattern 5/15 disposed on the second side surface and including at least one second lower bridge pattern 5 spaced apart from the substrate;
a second upper active pattern 5/10 disposed on the second side surface and including at least one second upper bridge pattern 5 spaced apart from the substrate than the second lower active pattern; and
a second gate structure 45 disposed on the second side surface and intersecting the second lower active pattern and the second upper active pattern,
wherein a width in the second direction of the wall structure 31 increases as the wall structure extends away from the substrate 1.
Regarding claim 2, Reboh discloses the semiconductor device of claim 1, wherein:
the at least one first lower bridge pattern is a plurality of lower sheet patterns 5 and the at least one first upper bridge pattern is a plurality of upper sheet patterns 5, and a width W1 in the second direction of each sheet pattern of the plurality of upper sheet patterns 5 is smaller than a width W2 in the second direction of each sheet pattern of the plurality of lower sheet patterns 5. See Fig. 1.
Regarding claim 16, Reboh discloses a semiconductor device comprising:
a substrate 1 (see Fig. 1, Fig. 4);
a wall structure 31 or 29 and 31 disposed on the substrate 1 and extending in a first direction (X-direction into the page of the drawing), wherein the wall structure includes a first side surface (left side surface) and a second side surface (right side surface) opposite to the first side surface in a second direction (Y-direction laterally to the sides of the page) intersecting the first direction;
a first lower active pattern 5 or 15 (fig. 4) disposed on the first side surface and including at least one first lower sheet pattern 5 spaced apart from the substrate 1;
a first upper active pattern 5 or 10 (fig. 4) disposed on the first side surface and including at least one first upper sheet pattern 5 spaced further apart from the substrate than the first lower active pattern;
a first gate structure 45 disposed on the first side surface and intersecting the first lower active pattern and the first upper active pattern;
a second lower active pattern 5/15 disposed on the second side surface and including at least one second lower sheet pattern 5 spaced apart from the substrate;
a second upper active pattern 5/10 disposed on the second side surface and including at least one second upper sheet pattern 5 spaced apart from the substrate than the second lower active pattern; and
a second gate structure 45 disposed on the second side surface and intersecting the second lower active pattern and the second upper active pattern,
wherein a width in the second direction of each sheet pattern 5/10 of the at least one first upper sheet pattern 5/10 is smaller than a width in the second direction of each sheet pattern 5/15 of the at least one first lower sheet pattern 5/15,
wherein a number of sheet patterns 5 (3 sheet patterns 5) in the at least one first upper sheet pattern is greater than a number of sheet patterns 5 (2 sheet patterns 5) in the at least one first lower sheet pattern.
Regarding claim 17, Reboh discloses the semiconductor device of claim 16, wherein a width in the second direction of the wall structure 31 increases as the wall structure extends away from the substrate. See Fig. 1.
Regarding claim 18, Reboh discloses the semiconductor device of claim 16, wherein a number of sheet patterns (3 sheet patterns) in the at least one second upper sheet pattern 5/10 is greater than a number of sheet patterns (2 sheet patterns) in the at least one second lower sheet pattern 5/15. See Fig. 1.
7. Claims 1, 3-5, 7-8, 11-13, 15-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2024/0312997)
Regarding claim 1, Lin discloses a semiconductor device comprising:
a substrate 100 (see Fig. 14A);
a wall structure 260 (para. 0066) disposed on the substrate 100 and extending in a first direction (X-direction), wherein the wall structure 260 includes a first side surface (left side surface) and a second side surface (right side surface) opposite to the first side surface in a second direction (Y-direction) intersecting the first direction;
a first lower active pattern 116A disposed on the first side surface and including at least one first lower bridge pattern 116A spaced apart from the substrate 100;
a first upper active pattern 116C disposed on the first side surface and including at least one first upper bridge pattern 116C spaced further apart from the substrate than the first lower active pattern 116A;
a first gate structure 150 disposed on the first side surface and intersecting the first lower active pattern 116A and the first upper active pattern 116C;
a second lower active pattern 216A disposed on the second side surface and including at least one second lower bridge pattern 216A spaced apart from the substrate 100;
a second upper active pattern 216C disposed on the second side surface and including at least one second upper bridge pattern 216C spaced apart from the substrate than the second lower active pattern 216A; and
a second gate structure 250 disposed on the second side surface and intersecting the second lower active pattern 216A and the second upper active pattern 216C,
wherein a width in the second direction of the wall structure 260 increases as the wall structure 260 extends away from the substrate 100.
Regarding claim 3, Lin discloses the semiconductor device of claim 1, wherein a third direction (Z-direction) intersects the first direction (X-direction) and the second direction (Y-direction), wherein a thickness 116t3 (Fig. 2A) in the third direction of each bridge pattern 116C of the at least one first upper bridge pattern 116C is greater than a thickness 116t1 in the third direction of each bridge pattern 116C of the at least one first lower bridge pattern (see paras. 0029-0033).
Regarding claim 4, Lin discloses the semiconductor device of claim 1, wherein a number of bridge patterns 116B & 116C of the at least one first upper bridge pattern 116B & 116C is greater than a number of bridge patterns 116A of the at least one first lower bridge pattern 116A. See fig. 14A.
Regarding claim 5, Lin discloses the semiconductor device of claim 1, further comprising a base insulating film 152 (covering the upper surfaces of the substrate 100 and isolation structure 115) disposed between the substrate 100 and the first lower active pattern 116A so as to electrically insulate the substrate 100 and the first lower active pattern 116A from each other. See Fig. 2A, Fig. 14A.
Regarding claim 7, Lin discloses the semiconductor device of claim 1, wherein the first gate structure 150 includes a gate dielectric film 152 and a gate electrode 154 sequentially stacked on the first lower active pattern 116A and the first upper active pattern 116B/116C, wherein a portion of the gate dielectric film 152 is interposed between the wall structure 260 and (a portion of) the gate electrode 154. See Fig. 14A.
Regarding claim 8, Lin discloses the semiconductor device of claim 1, further comprising:
a first lower source/drain pattern 140 (see Fig. 1) disposed on a side surface of the first gate structure 150 and contacting the first lower active pattern 116A in the first direction;
a first upper source/drain pattern 140 disposed on the side surface of the first gate structure 150 and contacting the first upper active pattern 116C in the first direction;
a second lower source/drain pattern 240 disposed on a side surface of the second gate structure 250 and contacting the second lower active pattern 216A in the first direction; and
a second upper source/drain pattern 240 disposed on the side surface of the second gate structure 250 and contacting the second upper active pattern 216C in the first direction. See Fig. 1.
Regarding claim 11, Lin discloses a semiconductor device comprising:
a substrate 100 (Fig. 14A);
a wall structure 260 (para. 0066) disposed on the substrate 100 and extending in a first direction (X-direction), wherein the wall structure 260 includes a first side surface (left side surface) and a second side surface (right side surface) opposite to the first side surface in a second direction (Y-direction) intersecting the first direction;
a first lower active pattern 116A disposed on the first side surface and including at least one first lower bridge pattern 116A spaced apart from the substrate 100;
a first upper active pattern 116C disposed on the first side surface and including at least one first upper bridge pattern 116C spaced further apart from the substrate than the first lower active pattern 116A;
a first gate structure 150 disposed on the first side surface and intersecting the first lower active pattern 116A and the first upper active pattern 116C;
a second lower active pattern 216A disposed on the second side surface and including at least one second lower bridge pattern 216A spaced apart from the substrate 100;
a second upper active pattern 216C disposed on the second side surface and including at least one second upper bridge pattern 216C spaced apart from the substrate than the second lower active pattern 216A; and
a second gate structure 250 disposed on the second side surface and intersecting the second lower active pattern 216A and the second upper active pattern 216C,
wherein a width in the second direction of each bridge pattern of the at least one first upper bridge pattern 116C is smaller than a width in the second direction of each bridge pattern of the at least one first lower bridge pattern 116A (see Fig. 14A, and para. 0028),
wherein a third direction (Z-direction) intersects the first direction (X-direction) and the second direction (Y-direction), wherein a thickness 116t3 (Fig. 2A) in the third direction of each bridge pattern 116C of the at least one first upper bridge pattern 116C is greater than a thickness 116t1 in the third direction of each bridge pattern 116C of the at least one first lower bridge pattern (see paras. 0029-0033).
Regarding claim 12, Lin discloses the semiconductor device of claim 11, wherein a width in the second direction of the wall structure 260 increases as the wall structure extends away from the substrate 100. See Fig. 14A.
Regarding claim 13, Lin discloses the semiconductor device of claim 11, wherein a thickness in the third direction of each bridge pattern 216B, 216C of the at least one second upper bridge pattern is greater than a thickness in the third direction of each bridge pattern 216A of the at least one second lower bridge pattern. See Fig. 14A.
Regarding claim 15, Lin discloses the semiconductor device of claim 11, wherein an area size of a cross section intersecting the first direction of the first upper active pattern 16C is equal to an area size of a cross section intersecting the first direction of the first lower active pattern 16A. See Fig. 14A.
Regarding claim 16, Lin discloses a semiconductor device comprising:
a substrate 100 (Fig. 14A);
a wall structure 260 (para. 0066) disposed on the substrate 100 and extending in a first direction (X-direction), wherein the wall structure 260 includes a first side surface (left side surface) and a second side surface (right side surface) opposite to the first side surface in a second direction (Y-direction) intersecting the first direction;
a first lower active pattern 116A disposed on the first side surface and including at least one first lower sheet pattern 116A spaced apart from the substrate 100;
a first upper active pattern 116C disposed on the first side surface and including at least one first upper sheet pattern 116B & 116C spaced further apart from the substrate than the first lower active pattern 116A;
a first gate structure 150 disposed on the first side surface and intersecting the first lower active pattern 116A and the first upper active pattern 116C;
a second lower active pattern 216A disposed on the second side surface and including at least one second lower sheet pattern 216A spaced apart from the substrate 100;
a second upper active pattern 216C disposed on the second side surface and including at least one second upper sheet pattern 216B & 216C spaced apart from the substrate than the second lower active pattern 216A; and
a second gate structure 250 disposed on the second side surface and intersecting the second lower active pattern 216A and the second upper active pattern 216C,
wherein a width in the second direction of each sheet pattern of the at least one first upper sheet pattern 116B & 116C is smaller than a width in the second direction of each sheet pattern of the at least one first lower sheet pattern 116A (see Fig. 14A, and para. 0028),
wherein a number of sheet patterns 116B & 116C in the at least one first upper sheet pattern is greater than a number of sheet patterns 116A in the at least one first lower sheet pattern.
Regarding claim 17, Lin discloses the semiconductor device of claim 16, wherein a width in the second direction (Y-direction) of the wall structure 260 increases as the wall structure extends away from the substrate 100. See Fig. 14A.
Regarding claim 18, Lin discloses the semiconductor device of claim 16, wherein a number of sheet patterns 216B & 216C in the at least one second upper sheet pattern is greater than a number of sheet patterns 216A in the at least one second lower sheet pattern. See Fig. 14A.
Regarding claim 20, Lin discloses the semiconductor device of claim 16, wherein an area size of a cross section intersecting the first direction (X-direction) of the first upper active pattern is equal to an area size of a cross section intersecting the first direction of the first lower active pattern. See Fig. 14A.
8. Claims 1, 5-6, 8-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Mazza et al. (US 2025/0194182)
Regarding claim 1, Mazza discloses a semiconductor device comprising:
a substrate 202 (see Figs. 5A, 5B);
a wall structure 236 (para. 0086) disposed on the substrate and extending in a first direction (X-direction), wherein the wall structure 236 includes a first side surface (left side surface) and a second side surface (right side surface) opposite to the first side surface in a second direction (Y-direction, Fig. 5B) intersecting the first direction;
a first lower active pattern 208-1 (under middle dielectric insulator MDI layer 206 and on the left side of the wall structure 236, see Fig. 4B, Fig. 5B) disposed on the first side surface and including at least one first lower bridge pattern 208-1 spaced apart from the substrate 202;
a first upper active pattern 208-2 disposed on the first side surface and including at least one first upper bridge pattern 208-2 spaced further apart from the substrate than the first lower active pattern 208-1;
a first gate structure 214 (Fig. 5B) disposed on the first side surface and intersecting the first lower active pattern and the first upper active pattern;
a second lower active pattern 208-1 (under middle dielectric insulator MDI layer 206 and on the right side of the wall structure 236, see Fig. 4B, Fig. 5B) disposed on the second side surface (right side surface) and including at least one second lower bridge pattern 208-1 spaced apart from the substrate;
a second upper active pattern 208-2 disposed on the second side surface and including at least one second upper bridge pattern 208-2 spaced apart from the substrate than the second lower active pattern; and
a second gate structure 214 disposed on the second side surface and intersecting the second lower active pattern 208-1 and the second upper active pattern 208-2,
wherein a width in the second direction (Y-direction) of the wall structure 236 increases as the wall structure 236 extends away from the substrate 202 (fig. 5B).
Regarding claim 5, Mazza discloses the semiconductor device of claim 1, further comprising a base insulating film 204 disposed between the substrate 202 and the first lower active pattern 208-1 so as to electrically insulate the substrate 202 and the first lower active pattern 208-1 from each other. See Figs. 5A-5B.
Regarding claim 6, Mazza discloses the semiconductor device of claim 1, further comprising a middle insulating film 206 disposed between the first lower active pattern 208-1 and the first upper active pattern 208-2 so as to electrically insulate the first lower active pattern and the first upper active pattern from each other. See Figs. 4A-B, 5A-B.
Regarding claim 8, Mazza discloses the semiconductor device of claim 1, further comprising:
a first lower source/drain pattern 222 disposed on a side surface of the first gate structure 214 and contacting the first lower active pattern 208-1 in the first direction;
a first upper source/drain pattern 224 disposed on the side surface of the first gate structure 214 and contacting the first upper active pattern 208-2 in the first direction;
a second lower source/drain pattern 222 disposed on a side surface of the second gate structure 214 and contacting the second lower active pattern 208-1 in the first direction; and
a second upper source/drain pattern 224 disposed on the side surface of the second gate structure 214 and contacting the second upper active pattern 208-2 in the first direction. See Figs. 4A-B, 5A-B.
Regarding claim 9, Mazza discloses the semiconductor device of claim 8, wherein each of the first lower source/drain pattern 222 and the first upper source/drain pattern 224 includes impurities of a first conductivity type, wherein each of the second lower source/drain pattern 222 and the second upper source/drain pattern 224 includes impurities of a second conductivity type different from the first conductivity type. See paras. 0019, 0026.
Regarding claim 10, Mazza discloses the semiconductor device of claim 8, wherein each of the first lower source/drain pattern and the second lower source/drain pattern includes impurities of a first conductivity type, wherein each of the first upper source/drain pattern and the second upper source/drain pattern includes impurities of a second conductivity type different from the first conductivity type. See paras. 0019, 0026.
Claim Rejections - 35 U.S.C. § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 2-3, 11-13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Mazza et al. (US 2025/0194182) in view of Lin et al. (US 2024/0312997)
Regarding claim 2, Mazza discloses the semiconductor device of claim 1, comprising all claimed limitations as discussed above, and further wherein:
the at least one first lower bridge pattern 208-1 is a plurality of lower sheet patterns 208-1 and the at least one first upper bridge pattern 208-2 is a plurality of upper sheet patterns 208-2, forming a stacked sheet patterns 208-1, 208-2.
Mazza fails to disclose:
a width in the second direction of each sheet pattern of the plurality of upper sheet patterns is smaller than a width in the second direction of each sheet pattern of the plurality of lower sheet patterns.
Lin discloses:
A semiconductor device comprising stacked plurality of active patterns 116A-116C and/or 216A-216C disposed on a substrate 100, wherein a width in a second direction (lateral direction parallel to an upper surface of the substrate 100) of the active patterns are getting smaller in a direction away from the upper surface of the substrate 100. See para. 0028.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Mazza so that the stacked active patterns or stacked sheet patterns of Mazza would get smaller in a direction away from the upper surface of the substrate, as that taught by Lin, in order to increase the effective channel width, thereby reducing the channel resistance of the bottom semiconductor nanosheet. See para. 0028 of Lin.
Regarding claim 3, Mazza discloses the semiconductor device of claim 1, comprising all claimed limitations, as discussed above, except for wherein a third direction intersects the first direction and the second direction, wherein a thickness in the third direction of each bridge pattern of the at least one first upper bridge pattern is greater than a thickness in the third direction of each bridge pattern of the at least one first lower bridge pattern.
Lin discloses:
A semiconductor device wherein a third direction (Z-direction) intersects the first direction (X-direction) and the second direction (Y-direction), wherein a thickness 116t2 or 116t3 in the third direction of each bridge pattern of the at least one first upper bridge pattern 116B or 116C is greater than a thickness 116t1 in the third direction of each bridge pattern of the at least one first lower bridge pattern 116A (see Fig. 2A and paras. 0029-0033). That is, Lin discloses the semiconductor device wherein the thicknesses of the upper bridge patterns are greater than the thicknesses of the lower bridge patterns.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Mazza so that the thickness of the upper bridge pattern(s) being greater than that/those of the lower bridge pattern(s), as that/those taught by Lin, in order to improve the short channel effect (SCE) control due to the excessive channel width that results in weaker gate control of the bottom or lower semiconductor nanosheet. See para. 0029 of Lin.
Regarding claim 11, Mazza discloses a semiconductor device comprising:
a substrate 202 (see Figs. 5A, 5B);
a wall structure 236 (para. 0086) disposed on the substrate and extending in a first direction (X-direction), wherein the wall structure 236 includes a first side surface (left side surface) and a second side surface (right side surface) opposite to the first side surface in a second direction (Y-direction, Fig. 5B) intersecting the first direction;
a first lower active pattern 208-1 (under middle dielectric insulator MDI layer 206 and on the left side of the wall structure 236, see Fig. 4B, Fig. 5B) disposed on the first side surface and including at least one first lower bridge pattern 208-1 spaced apart from the substrate 202;
a first upper active pattern 208-2 disposed on the first side surface and including at least one first upper bridge pattern 208-2 spaced further apart from the substrate than the first lower active pattern 208-1;
a first gate structure 214 (Fig. 5B) disposed on the first side surface and intersecting the first lower active pattern and the first upper active pattern;
a second lower active pattern 208-1 (under middle dielectric insulator MDI layer 206 and on the right side of the wall structure 236, see Fig. 4B, Fig. 5B) disposed on the second side surface (right side surface) and including at least one second lower bridge pattern 208-1 spaced apart from the substrate;
a second upper active pattern 208-2 disposed on the second side surface and including at least one second upper bridge pattern 208-2 spaced apart from the substrate than the second lower active pattern; and
a second gate structure 214 disposed on the second side surface and intersecting the second lower active pattern 208-1 and the second upper active pattern 208-2.
Mazza fails to disclose:
wherein a width in the second direction of each bridge pattern of the at least one first upper bridge pattern is smaller than a width in the second direction of each bridge pattern of the at least one first lower bridge pattern,
wherein a third direction intersects the first direction and the second direction, wherein a thickness in the third direction of each bridge pattern of the at least one first upper bridge pattern is greater than a thickness in the third direction of each bridge pattern of the at least one first lower bridge pattern.
Lin discloses:
A semiconductor device comprising stacked plurality of bridge patterns 116A-116C and/or 216A-216C disposed on a substrate 100, wherein a width in a second direction (lateral direction parallel to an upper surface of the substrate 100) of the bridge patterns are getting smaller in a direction away from the upper surface of the substrate 100. See para. 0028; and
wherein a third direction (Z-direction) intersects the first direction (X-direction) and the second direction (Y-direction), wherein a thickness 116t2 or 116t3 in the third direction of each bridge pattern of the at least one first upper bridge pattern 116B or 116C is greater than a thickness 116t1 in the third direction of each bridge pattern of the at least one first lower bridge pattern 116A (see Fig. 2A and paras. 0029-0033). That is, Lin discloses the semiconductor device wherein the thicknesses of the upper bridge patterns are greater than the thicknesses of the lower bridge patterns.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Mazza so that the stacked active patterns or stacked sheet patterns of Mazza would get smaller in a direction away from the upper surface of the substrate, as that taught by Lin, in order to increase the effective channel width, thereby reducing the channel resistance of the bottom semiconductor nanosheet. See para. 0028 of Lin.
In addition, it would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Mazza so that the thickness of the upper bridge pattern(s) being greater than that/those of the lower bridge pattern(s), as that/those taught by Lin, in order to improve the short channel effect (SCE) control due to the excessive channel width that results in weaker gate control of the bottom or lower semiconductor nanosheet. See para. 0029 of Lin.
Regarding claim 12, Mazza/Lin discloses the semiconductor device of claim 11, wherein a width in the second direction of the wall structure 236 increases as the wall structure extends away from the substrate 202. See fig. 5B of Mazza.
Regarding claim 13, Mazza/Lin discloses the semiconductor device of claim 11, wherein a thickness in the third direction of each bridge pattern of the at least one second upper bridge pattern is greater than a thickness in the third direction of each bridge pattern of the at least one second lower bridge pattern. See the rejection of claim 11.
Regarding claim 15, Mazza/Lin discloses the semiconductor device of claim 11, wherein an area size of a cross section intersecting the first direction of the first upper active pattern is equal to an area size of a cross section intersecting the first direction of the first lower active pattern. See fig. 5B of Mazza.
Allowable Subject Matter
11. Claims 14 and 19 are allowable.
Claims 14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed semiconductor device (in addition to the other limitations in the claim) comprising:
Claim 14:
wherein a spacing in the third direction between the first upper sheet pattern and the second upper sheet pattern is smaller than a spacing in the third direction between the first lower sheet pattern and the second lower sheet pattern.
Claim 19:
wherein a spacing between the upper sheet pattern and the adjacent upper sheet pattern in a third direction perpendicular to the first direction and the second direction is smaller than a spacing between the lower sheet pattern and the adjacent lower sheet pattern in the third direction.
Conclusion
12. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 August 13, 2026
Prosecution Insights