DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al., (United States Patent Number, US 9,875,911 B2) hereinafter referenced as Pagaila, in view of Shih, (United States Patent Application Publication Number, US 2021/0050327 A1) hereinafter referenced as Shih, in view of Dunne et al., (United States Patent Number, US 8,313,982 B2) hereinafter referenced as Dunne, in view of Takeda et al., (United States Patent Application Publication Number, US 2013/0252416 A1) hereinafter referenced as Takeda and in view of Chen et al., (United States Patent Application Publication Number, US 2019/0103386 A1) hereinafter referenced as Chen_386.
Regarding claim 1, Pagaila teaches a semiconductor package comprising: a redistribution structure (Fig.15, element #274. Note that Fig.12 and Fig.15 represent different package arrangements of similar components, and structure shown in Fig.12 can be attached to the redistribution layer of Fig.15) a lower semiconductor device arranged on the redistribution structure (Fig.12, element #134) and including a plurality of first through electrodes each having a first horizontal width (Fig.12, element 232); a connecting substrate arranged on the redistribution structure and spaced apart from the lower semiconductor device in a horizontal direction (Fig.12, element #149), wherein the connecting substrate includes a plurality of second through electrodes each having a second horizontal width (Fig.12, elements #122).
Pagaila does not teach the second horizontal width is greater than the first horizontal width. Shih teaches a lower semiconductor device arranged on a redistribution structure including a plurality of first electrodes (Fig.13, elements #110) and a connecting substrate includes a plurality of second through electrodes each having a second horizontal width (Fig.13, elements #510), greater than the first horizontal width (paragraph [0039], rows 5-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Shih and disclose a lower semiconductor device arranged on a redistribution structure including a plurality of first electrodes and the connecting substrate includes a plurality of second through electrodes each having a second horizontal width, greater than the first horizontal width. As disclosed by Shih, the second through electrodes may transmit power, and their larger diameter provide less resistance and improved signal integrity as compared to the lower diameter first electrodes (paragraph [0060], rows 4-8).
Pagaila further teaches a first molding layer arranged on the redistribution structure and surrounding a side surface of the lower semiconductor device and a side surface of the connecting substrate (Fig.12, element #140, numbered in Fig.3e); and an upper semiconductor device arranged on the lower semiconductor device and the connecting substrate, the upper semiconductor device electrically connected to the plurality of first through electrodes of the lower semiconductor device and the plurality of second through electrodes of the connecting substrate (Fig.12, element #132).
The combination of Pagaila and Shih does not teach wherein a plane area of the upper semiconductor device is greater than a plane area of the lower semiconductor device. Dunne teaches a plane area of the upper semiconductor device is greater than a plane area of the lower semiconductor device (Fig.3A, upper semiconductor device, element #310, has a greater plane area than a plane area of lower semiconductor device, element #210, column 8, rows 26-28). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Dunne and disclose wherein a plane area of the upper semiconductor device is greater than a plane area of the lower semiconductor device. A greater plane area of the upper semiconductor device, which faces the lower semiconductor device, allows connecting multiple portions of the area of the upper semiconductor device to multiple devices and/or connecting substrates, thus increasing package functionality and connection flexibility.
The combination of Pagaila, Shih and Dunne does not teach wherein the first horizontal width is about 1µm to about 7µm and the second horizontal width is about 10µm to about 20µm. Takeda teaches a semiconductor die with through interconnects with a horizontal width of 3 µm (Fig.40, element #16, paragraph [203], rows 6-8, Fig.27 the vias a through vias). The claimed range, between 1µm and 7µm overlaps with the values disclosed by England and therefore a prima facie case of obviousness exists (MPEP 2144.05). Chen_386 teaches the second horizontal width is between 1µm to 20µm (Fig.15, element # paragraph [0098], rows 20-24). The claimed range, between 10µm and20 µm overlaps or lies inside the range disclosed by Chen_386 and therefore a prima facie case of obviousness exists (MPEP 2144.05). Making the first electrodes with a horizontal width between 1µm and 7µm minimizes the volume occupied by the vias, which allows more space for other circuit elements of the device, while making the second electrodes with a horizontal width between 10µm and 20µm allow the transmission of power and or signals to the upper semiconductor device while providing less resistance and maintaining signal integrity.
Regarding claim 2, the combination of Pagaila, Shih, Dunne, Takeda, and Chen_386 teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Pagaila further teaches the semiconductor package of claim 1, further comprising a heat dissipation member on the upper semiconductor device (Fig.6, element #180).
Regarding claim 3, the combination of Pagaila, Shih, Dunne, Takeda, and Chen_386 teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Pagaila further teaches the semiconductor package of claim 1, wherein the connecting substrate further comprises a base layer, the plurality of second through electrodes pass through the base layer, and the first molding layer is in contact with a side surface of the base layer (Fig.12, the connecting substrate, element #149, has a based layer made of semiconductor, element #118, and the molding, element #140 is in contact with its side surface).
Regarding claim 5, the combination of Pagaila, Shih, Dunne, Takeda, and Chen_386 teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Pagaila further teaches the semiconductor package of claim 1, wherein side surfaces of the upper semiconductor device are aligned with side surfaces of the first molding layer in a vertical direction (Fig.12, side surfaces of element #132 and side surfaces of the molding are vertical, so they are aligned in the vertical direction).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Pagaila in view of Shih, Dunne, Takeda, Chen_386 and in view of Mahajan et al., (United States Patent Application Publication Number, US 2020/0286814 A1) hereinafter referenced as Mahajan.
Regarding claim 4, the combination of Pagaila, Shih, Dunne, Takeda, and Chen_386 teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. The combination of Pagaila, Shih, Dunne, Takeda, and Chen_386 does not teach the semiconductor package of claim 1, wherein the plane area of the upper semiconductor device is greater than a sum of the plane area of the lower semiconductor device and a plane area of the connecting substrate. Mahajan teaches wherein the plane area of the upper semiconductor device is greater than a sum of the plane area of the lower semiconductor device and a plane area of the connecting substrate (Fig.1H and 1I, upper semiconductor device is element #130, lower semiconductor device is element #120, connecting substrate includes part of element #105 containing only the two vias #107 located on the right side of element #120 in Fig.1H). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Mahajan and disclose the plane area of the upper semiconductor device is greater than a sum of the plane area of the lower semiconductor device and a plane area of the connecting substrate. This allows connecting all the first and second electrodes to the plane area of the upper semiconductor device, and increases connection flexibility.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Pagaila in view of Shih, Dunne, Takeda, Chen_386 and in view of Jeng et al., (United States Patent Application Publication Number, US 2019/0131241 A1) hereinafter referenced as Jeng.
Regarding claim 6, the combination of Pagaila, Shih, Dunne, Takeda, and Chen_386 teaches the semiconductor package of claims 1 and 5 as set forth in the obviousness rejection. Pagaila further teaches the semiconductor package of claim 5, wherein one side surface of the connecting substrate is not covered by the first molding layer, and is exposed to outside (Fig.15, left side surface of the connecting substrate is not covered by molding). The combination of Pagaila, Shih, Dunne, Takeda, and Chen_386 does not teach the one side surface of the connecting substrate is on a same plane as one side surface of the upper semiconductor device. Jeng teaches wherein one side surface of the connecting substrate is not covered by the first molding layer and is exposed to outside (Fi.1K, left side surface of element #112 is exposed to outside), and the one side surface of the connecting substrate is on a same plane as one side surface of the upper semiconductor device (Fig.1K, the left side surfaces of element #122 and #134 are on the same plane). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Jeng and disclose wherein one side surface of the connecting substrate is not covered by the first molding layer, and is exposed to outside, and the one side surface of the connecting substrate is on a same plane as one side surface of the upper semiconductor device. This ensures a smooth and continuous package side surface, without and corners or protrusions that may be subject to chipping during further package processing.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Pagaila in view of Shih, Dunne, Takeda, Chen_386 and in view of Yu et al., (United States Patent Application Publication Number, US 2015/0235989 A1) hereinafter referenced as Yu.
Regarding claim 7, the combination of Pagaila, Shih, Dunne, Takeda and Chen_386 teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Pagaila further teaches the semiconductor package of claim 1, further comprising: a plurality of first upper connection bumps electrically connecting the upper semiconductor device to the plurality of first through electrodes (Fig.12, element #136 located on top of the lower semiconductor device); and a plurality of second upper connection bumps electrically connecting the upper semiconductor device to the plurality of second through electrodes (Fig.12, element #136 located on top of the connecting substrate, element #149). The combination of Pagaila, Shih, Dunne, Takeda, and Chen_386 does not teach wherein a horizontal width of each of the plurality of second upper connection bumps is greater than a horizontal width of each of the plurality of first upper connection bumps. Yu teaches wherein a horizontal width of each of the plurality of second upper connection bumps is greater than a horizontal width of each of the plurality of first upper connection bumps (Fig.1K, a horizontal width of element #26 is greater than the horizontal width of element #24’, labeled in Fig.1F). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yu and disclose wherein a horizontal width of each of the plurality of second upper connection bumps is greater than a horizontal width of each of the plurality of first upper connection bumps. As disclosed by Yu in Fig.1K, the wider second connection bumps correspond to wider second electrodes and using wider connection bumps increased the reliability of electrical connections with the second electrodes. The narrower first connection bumps allow one to increase the density of first electrodes in the lower semiconductor device, while being able to connect each individual electrode with a corresponding first connection bump without shorting the electrodes.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Pagaila in view of Shih, Dunne, Takeda, Chen_386, Yu and in view of Arvin et al., (United States Patent Application Publication Number, US 2021/0057341 A1) hereinafter referenced as Arvin.
Regarding claim 8, the combination of Pagaila, Shih, Dunne, Takeda, and Chen_386 teaches the semiconductor package of claim 1 as set forth in the obviousness rejection and the combination of Pagaila, Shih, Dunne, Takeda, Chen_386 and Yu teaches the semiconductor package of claim 7 as set forth in the obviousness rejection. Pagaila further teaches the semiconductor package of claim 7, wherein the lower semiconductor device comprises a plurality of first upper bump pads to which the plurality of first upper connection bumps are attached, respectively (Fig.12, element #134 has pads attached to bumps #136), wherein the connecting substrate comprises a plurality of second upper bump pads to which the plurality of second upper connection bumps are attached (Fig.12, element #149 has pads attached to bumps #136). The combination of Pagaila, Shih, Dunne, Takeda, Chen_386 and Yu does not teach wherein a horizontal width of each of the plurality of second upper bump pads is greater than a horizontal width of each of the plurality of first upper bump pads. Arvin teaches a horizontal width of each of the plurality of second upper bump pads is greater than a horizontal width of each of the plurality of first upper bump pads (Fig.3, a horizontal width of elements #26 and greater than a horizontal width of elements #28). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Arvin and disclose a horizontal width of each of the plurality of second upper bump pads is greater than a horizontal width of each of the plurality of first upper bump pads. Wider second bump pads allow for more reliable electrical contacts, while narrower first bump pads allow one to increase the density of first electrodes in the lower semiconductor device, while being able to connect each individual electrode with a corresponding first bump pad.
Claim 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila in view of Shih, Dunne, Takeda, Chen_386, Yu and in view of Chen et al., (United States Patent Application Publication Number, US 2016/0035709 A1) hereinafter referenced as Chen_709.
Regarding claim 9, the combination of Pagaila, Shih, Dunne, Takeda, and Chen_386 teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. The combination of Pagaila, Shih, Dunne, Takeda, and Chen_386 does not teach the semiconductor package of claim 1, wherein the redistribution structure further comprises: a redistribution insulation layer; a plurality of first lower bump pads electrically connected to the plurality of first through electrodes, respectively, the plurality of first lower bump pads at least partially protruding from the redistribution insulation layer; and a plurality of second lower bump pads electrically connected to the plurality of second through electrodes, respectively, the plurality of second lower bump pads at least partially protruding from the redistribution insulation layer, and wherein a horizontal width of each of the plurality of second lower bump pads is greater than a horizontal width of each of the plurality of first lower bump pads. Chen_709 teaches wherein the redistribution structure further comprises: a redistribution insulation layer (Fig.26, layer covering top element #110, must be insulating, otherwise elements #110 will short); a plurality of first lower bump pads electrically connected to the plurality of first through electrodes, respectively, the plurality of first lower bump pads at least partially protruding from the redistribution insulation layer (Fig.26, elements #106 have pads on top, below the lower semiconductor device, element #118; note that Pagaila discloses the first through electrode in Fig.15. Lower is interpreted as lower than the upper semiconductor device in the vertical direction); and a plurality of second lower bump pads electrically connected to the plurality of second through electrodes, respectively, the plurality of second lower bump pads at least partially protruding from the redistribution insulation layer (Fig.26, element #102 protrude from the layer the cover top elements #110), and wherein a horizontal width of each of the plurality of second lower bump pads is greater than a horizontal width of each of the plurality of first lower bump pads (Fig.26, horizontal width of element #120 is greater). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Chen_709 and disclose wherein the redistribution structure further comprises: a redistribution insulation layer; a plurality of first lower bump pads electrically connected to the plurality of first through electrodes, respectively, the plurality of first lower bump pads at least partially protruding from the redistribution insulation layer; and a plurality of second lower bump pads electrically connected to the plurality of second through electrodes, respectively, the plurality of second lower bump pads at least partially protruding from the redistribution insulation layer, and wherein a horizontal width of each of the plurality of second lower bump pads is greater than a horizontal width of each of the plurality of first lower bump pads. Wider second bump pads allow for more reliable electrical connections with the second electrodes which are wider than the first electrodes, while narrower first bump pads allow one to increase the density of first electrodes in the lower semiconductor device, while being able to connect each individual electrode with a corresponding first bump pad.
Regarding claim 10, the combination of Pagaila, Shih, Dunne, Takeda, and Chen_386 teaches the semiconductor package of claim 1 as set forth in the obviousness rejection and the combination of Pagaila, Shih, Dunne, Takeda, Chen_386 and Chen_709 teaches the semiconductor package of claim 9 as set forth in the obviousness rejection. Chen_709 further teaches the semiconductor package of claim 9, further comprising: a plurality of first lower connection bumps on the plurality of first lower bump pads, respectively (Fig.26, element #120); and a plurality of second lower connection bumps on the plurality of second lower bump pads (Fig.26, element #174), respectively, wherein a horizontal width of each of the plurality of second lower connection bumps is different from a horizontal width of each of the plurality of first lower connection bumps (Fig.26, horizontal width of elements #174 is greater than the horizontal width of element #120). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Chen_709 and disclose a plurality of first lower connection bumps on the plurality of first lower bump pads, respectively, and a plurality of second lower connection bumps on the plurality of second lower bump pads, respectively, wherein a horizontal width of each of the plurality of second lower connection bumps is different from a horizontal width of each of the plurality of first lower connection bumps. Since the second connection bump pads are wider that the first connection bump pads, as noted in the rejection of claim 9, one can use second connection bumps wider than the first connection bumps. Using wider connection bumps increased the reliability of electrical connections with the second electrodes, while narrower first connection bumps allow one to increase the density of first electrodes in the lower semiconductor device, while being able to connect each individual electrode with a corresponding first connection bump pad without shorting the electrodes.
Claim 11-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila in view of Shih, Karhade et al, (United States Patent Application Publication Number, US 2015/0228583 A1) hereinafter referenced as Karhade and in view of Takeda and Chen_386.
Regarding claim 11, Pagaila teaches a semiconductor package comprising: a package substrate (Fig.2c, element 52); a redistribution structure arranged on the package substrate and electrically connected to the package substrate (Fig.2c, element#106); a lower semiconductor device arranged on the redistribution structure (Fig.15, element #260. Note that Fig.3a through 19 represent different package arrangements of similar components in relation to Fig.2c, and can be attached to the substrate of Fig.2c) and including a plurality of first through electrodes each having a first horizontal width (Fig.15, elements #292); a connecting substrate arranged on the redistribution structure and spaced apart from the lower semiconductor device in a horizontal direction (Fig.15, element #244), wherein the connecting substrate includes a plurality of second through electrodes each having a second horizontal width (Fig.15, elements #248).
Pagaila does not teach the second horizontal width is greater than the first horizontal width. Shih teaches a lower semiconductor device arranged on the redistribution structure including a plurality of first electrodes (Fig.13, elements #110) and the connecting substrate includes a plurality of second through electrodes each having a second horizontal width (Fig.13, elements #510), greater than the first horizontal width (paragraph [0039], rows 5-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Shih and disclose a lower semiconductor device arranged on the redistribution structure including a plurality of first electrodes and the connecting substrate includes a plurality of second through electrodes each having a second horizontal width, greater than the first horizontal width. As disclosed by Shih, the second through electrodes may transmit power, and their larger diameter provide less resistance and improved signal integrity as compared to the lower diameter first electrodes (paragraph [0060], rows 4-8).
Pagaila further teaches a first molding layer arranged on the redistribution structure and surrounding a side surface of the lower semiconductor device and a side surface of the connecting substrate (Fig.15, element #270); an upper semiconductor device arranged on the lower semiconductor device and the connecting substrate, the upper semiconductor device electrically connected to the plurality of first through electrodes of the lower semiconductor device and the plurality of second through electrodes of the connecting substrate (Fig.15, element #252).
The combination of Pagaila and Shih a second molding layer arranged on the package substrate and surrounding side surfaces of the first molding layer and covering at least parts of side surfaces of the upper semiconductor device. Karhade teaches a second molding layer arranged on the package substrate and surrounding side surfaces of the first molding layer and covering at least parts of side surfaces of the upper semiconductor device (Fig.6, element #618 is arranged on substrate, element #602, and surrounds the leftmost and rightmost side surfaces of element #616, and cover the side surface of the upper semiconductor device, element #608). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Karhade and disclose a second molding layer arranged on the package substrate and surrounding side surfaces of the first molding layer and covering at least parts of side surfaces of the upper semiconductor device. AS shown in Fig.6 of Karhade, the second molding protects the sidewalls of the connecting substrate and the upper semiconductor device from environmental damage and secures the assembly formed by the two devices and the connecting substrate to the substrate, thus increasing the mechanical stability of the entire structure.
The combination of Pagaila and Shih does not teach wherein a plane area of the upper semiconductor device is greater than a plane area of the lower semiconductor device. Karhade teaches a plane area of the upper semiconductor device is greater than a plane area of the lower semiconductor device (paragraph [0037], rows 6-8). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Karhade and disclose wherein a plane area of the upper semiconductor device is greater than a plane area of the lower semiconductor device. A greater plane area of the upper semiconductor device, which faces the lower semiconductor device, allows connecting multiple portions of the area of the upper semiconductor device to multiple devices and/or connecting substrates, thus increasing package functionality and connection flexibility.
The combination of Pagaila, Shih and Karhade does not teach wherein the first horizontal width is about 1µm to about 7µm and the second horizontal width is about 10µm to about 20µm. Takeda teaches a semiconductor die with through interconnects with a horizontal width of 3µm (Fig.40, element #16, paragraph [203], rows 6-8, Fig.27 the vias a through vias). The claimed range, between 1µm and 7µm overlaps with the values disclosed by England and therefore a prima facie case of obviousness exists (MPEP 2144.05). Chen_386 teaches the second horizontal width is between 1µm to 20µm (Fig.15, element # paragraph [0098], rows 20-24). The claimed range, between 10µm and20 µm overlaps or lies inside the range disclosed by Chen_386 and therefore a prima facie case of obviousness exists (MPEP 2144.05). Making the first electrodes with a horizontal width between 1µm and 7µm minimizes the volume occupied by the vias, which allows more space for other circuit elements of the device, while making the second electrodes with a horizontal width between 10µm and 20µm allow the transmission of power and or signals to the upper semiconductor device while providing less resistance and maintaining signal integrity.
Regarding claim 12, the combination of Pagaila, Shih, Karhade, Takeda, and Chen_386 teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Pagaila further teaches the semiconductor package of claim 11, further comprising a heat dissipation member on the upper semiconductor device (Fig.6, element #180).
Regarding claim 13, the combination of Pagaila, Shih, Karhade, Takeda, and Chen_386 teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Pagaila further teaches the semiconductor package of claim 11, wherein the connecting substrate further comprises a base layer, the plurality of second through electrodes pass through the base layer, and the first molding layer is in contact with a side surface of the base layer (Fig.15, the connecting substrate, element #244, has a based layer, element #246, and the molding, element #270 is in contact with its side surface).
Regarding claim 15, the combination of Pagaila, Shih, Karhade, Takeda, and Chen_386 teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Pagaila further teaches the semiconductor package of claim 11, wherein side surfaces of the upper semiconductor device are aligned with side surfaces of the first molding layer in a vertical direction (Fig.15, side surfaces of element #252 and side surfaces of the molding are vertical, so they are aligned in the vertical direction).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Pagaila in view of Shih, Karhade, Takeda and Chen_386 and in view of Mahajan.
Regarding claim 14, the combination of Pagaila, Shih, Karhade, Takeda, and Chen_386 teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. The combination of Pagaila, Shih, Karnade, Takeda, and Chen_386 does not teach the semiconductor package of claim 11, wherein the plane area of the upper semiconductor device is greater than a sum of the plane area of the lower semiconductor device and a plane area of the connecting substrate. Mahajan teaches wherein the plane area of the upper semiconductor device is greater than a sum of the plane area of the lower semiconductor device and a plane area of the connecting substrate (Fig.1H and 1I, upper semiconductor device is element #130, lower semiconductor device is element #120, connecting substrate includes part of element #105 containing only the two vias #107 located on the right side of element #120 in Fig.1H). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Mahajan and disclose the plane area of the upper semiconductor device is greater than a sum of the plane area of the lower semiconductor device and a plane area of the connecting substrate. This allows connecting all the first and second electrodes to the plane area of the upper semiconductor device, and increases connection flexibility.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila in view of Shih, Karhade, Takeda and Chen_386 and in view of Chien et al, (United States Patent Application Publication Number, US 2020/0395281 A1) hereinafter referenced as Chien.
Regarding claim 16, the combination of Pagaila, Shih, Karhade, Takeda, and Chen_386 teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Shih teaches the semiconductor package of claim 11, wherein the redistribution structure (Fig.13, element #700) further comprises: a redistribution insulation layer (Fig.13, element #712); a plurality of first lower bump pads electrically connected to the plurality of first through electrodes (Fig.13, elements #718 connected to elements #110), respectively, the plurality of first lower bump pads at least partially protruding from the redistribution insulation layer (Fig.13, elements #718 protrude from elements #712); and a plurality of second lower bump pads electrically connected to the plurality of second through electrodes(Fig.13, elements #718 connected to elements #510), respectively, the plurality of second lower bump pads at least partially protruding from the redistribution insulation layer (Fig.13, elements #718 protrude from elements #712). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Shih and disclose wherein the redistribution structure further comprises: a redistribution insulation layer; a plurality of first lower bump pads electrically connected to the plurality of first through electrodes, respectively, the plurality of first lower bump pads at least partially protruding from the redistribution insulation layer; and a plurality of second lower bump pads electrically connected to the plurality of second through electrodes, respectively, the plurality of second lower bump pads at least partially protruding from the redistribution insulation layer. The pads allow the connection of the redistribution layer to a substrate, such as a PCB, which can be used to power the semiconductor devices.
The combination of Pagaila, Shih, Karhade, Takeda, and Chen_386 does not teach wherein a horizontal width of each of the plurality of second lower bump pads is greater than a horizontal width of each of the plurality of first lower bump pads. Chien teaches wherein a horizontal width of each of the plurality of second lower bump pads is greater than a horizontal width of each of the plurality of first lower bump pads (Fig.19, the top horizontal width of the plurality of second lower bump pads, the three elements #1102 located on the left side of the figure, is greater than the bottom horizontal width of each of the plurality of first lower bump pads, the elements #1102 located in the middle of the figure). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Chien and disclose wherein a horizontal width of each of the plurality of second lower bump pads is greater than a horizontal width of each of the plurality of first lower bump pads. Wider second bump pads allow for more reliable electrical contacts with a package substrate, while narrower first bump pads allow one to increase the density of first electrodes in the lower semiconductor device, while being able to connect each individual electrode with a corresponding first bump pad and the package substrate.
Regarding claim 17, the combination of Pagaila, Shih, Karhade, Takeda, and Chen_386 teaches the semiconductor package of claim 11 as set forth in the obviousness rejection and the combination of Pagaila, Shih, Karhade, Takeda, Chen_386 and Chien teaches the semiconductor package of claim 16 as set forth in the obviousness rejection. Pagaila further teaches the semiconductor package of claim 16, wherein the lower semiconductor device and the connecting substrate are directly in contact with the redistribution insulation layer of the redistribution structure (Fig.15, elements #244 and #260 are in direct contact with element #274).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila in view of Takeda and Chen_386.
Regarding claim 18, Pagaila teaches a semiconductor package comprising: a redistribution structure arranged on the package substrate and electrically connected to the package substrate (Fig.2c, element#106); a lower semiconductor device arranged on the redistribution structure (Fig.15, element #260) and including a plurality of first through electrodes each having a first horizontal width (Fig.15, elements #292); a connecting substrate arranged on the redistribution structure and spaced apart from the lower semiconductor device in a horizontal direction (Fig.15, element #244), wherein the connecting substrate includes a plurality of second through electrodes each having a second horizontal width (Fig.15, elements #248), a first molding layer arranged on the redistribution structure and surrounding a side surface of the lower semiconductor device and a side surface of the connecting substrate (Fig.15, element #270); an upper semiconductor device arranged on the lower semiconductor device and the connecting substrate, the upper semiconductor device electrically connected to the plurality of first through electrodes of the lower semiconductor device and the plurality of second through electrodes of the connecting substrate (Fig.15, element #252), wherein the lower semiconductor device and the connecting substrate are directly in contact with the redistribution structure (fig.15, element #260 and #244 are in direct contact with elements #274), side surfaces of the upper semiconductor device are aligned with side surfaces of the first molding layer in a vertical direction (Fig.15, side surfaces of element #232 and side surfaces of the molding, element #270 are vertical, so they are aligned in the vertical direction).
Pagaila does not teach wherein the first horizontal width is about 1µm to about 7µm and the second horizontal width is about 10µm to about 20µm. Takeda teaches a semiconductor die with through interconnects with a horizontal width of 3µm (Fig.40, element #16, paragraph [203], rows 6-8, Fig.27 the vias a through vias). The claimed range, between 1µm and 7µm overlaps with the values disclosed by England and therefore a prima facie case of obviousness exists (MPEP 2144.05). Chen_386 teaches the second horizontal width is between 1µm to 20µm (Fig.15, element # paragraph [0098], rows 20-24). The claimed range, between 10µm and20 µm overlaps or lies inside the range disclosed by Chen_386 and therefore a prima facie case of obviousness exists (MPEP 2144.05). Making the first electrodes with a horizontal width between 1µm and 7µm minimizes the volume occupied by the vias, which allows more space for other circuit elements of the device, while making the second electrodes with a horizontal width between 10µm and 20µm allow the transmission of power and or signals to the upper semiconductor device while providing less resistance and maintaining signal integrity.
Regarding claim 19, the combination of Pagaila, Takeda, and Chen_386 teaches the semiconductor package of claim 18 as set forth in the obviousness rejection. Pagaila further teaches the semiconductor package of claim 18, wherein the lower semiconductor device further comprises a first semiconductor substrate including a first surface facing the upper semiconductor device and a second surface opposite to the first surface, and a first semiconductor device layer arranged on the first surface of the first semiconductor substrate or the second surface of the first semiconductor substrate (Fig.15, element #260 is a semiconductor die with a device surface, bottom surface element #262, column 13, rows 23-25, therefore comprises a semiconductor substrate with the top surface facing the upper semiconductor device) the plurality of first through electrodes pass through the first semiconductor substrate (Fig.15, elements #292 pass through the entire depth of the die, so they pass through the substrate), the connecting substrate further comprises a base layer (Fig.15, elements #246), and the plurality of second through electrodes pass through the base layer (Fig.15, second electrodes pass through element #246).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Pagaila in view of Takeda, Chen_386 and Chen et al., (United States Patent Application Publication Number, US 2013/0182402 A1), hereinafter referenced as Chen_402.
Regarding claim 20, the combination of Pagaila, Takeda, and Chen_386 teaches the semiconductor package of claim 18 as set forth in the obviousness rejection. Pagaila further teaches the semiconductor package of claim 18, further comprising a heat dissipation member on the upper semiconductor device (Fig.6, element #180). The combination of Pagaila, Takeda, and Chen_386 does not teach wherein the upper semiconductor device generates an amount of heat greater than an amount of heat generated by the lower semiconductor device.
Chen_402 teaches the upper semiconductor die may include a CPU and the lower semiconductor dies may include memories (Fig.11, elements #24 and #64 are swapped and element #24 may be a CPU paragraph [0009], rows 17-20, and elements #64 may be memories die, paragraph [0020], rows 1-4). CPUs are known to generate an amount of heat greater than the amount of heat generated by memories, and therefore Chen_402 teaches wherein the upper semiconductor device generates an amount of heat greater than an amount of heat generated by the lower semiconductor device. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Chen_402 and disclose the upper semiconductor device generates an amount of heat greater than an amount of heat generated by the lower semiconductor device. As disclosed by Pagaila, the heat dissipation member is in contact with the upper semiconductor device (Fig.6). Therefore, having the device generating the larger amount of heat as the upper semiconductor device will improve head dissipation away from the package.
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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