Prosecution Insights
Last updated: August 17, 2026
Application No. 18/800,342

IMAGE SENSOR

Non-Final OA §103§112
Filed
Aug 12, 2024
Priority
Aug 21, 2023 — FR 2308824
Examiner
REAMES, MATTHEW L
Art Unit
Tech Center
Assignee
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
848 granted / 1101 resolved
+17.0% vs TC avg
Strong +18% interview lift
Without
With
+18.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
50 currently pending
Career history
1128
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
43.2%
+3.2% vs TC avg
§102
18.1%
-21.9% vs TC avg
§112
33.3%
-6.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1101 resolved cases

Office Action

§103 §112
DETAILED ACTION DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claim 5.5 6 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Applicant gives no specifics as to how to form one photodiode in a on substrate and the pinned area in a second beyond a black box approach. As to claim 5 does not show how to form a hybridized device with parts in different substrates. As to claim 6, the interconnects are not shown. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. a. It is unclear if each pixel includes a metal connecting element and a pinned area. As claimed the device only comprises the pixels. It appears applicant means to recite An image sensor comprising a plurality of pixels, each pixel including a non-pinned photodiode; the image sensor further comprising: a metal connecting element; a pinned area formed in a first semiconductor substrate wherein the non-pinned photodiode is connected by the metal connecting element to the pinned area. Further a pinned area is unclear and confusing a pinned photodiode has a surface layer which is the same conductivity as substrate so the surface is connected to the ground of the substrate. So, in affect the photodiode has too grounded surfaces a top grounded surface and a bottom grounded. It has been given a specific name to distinguish it from the photo diode that do not have this surface connection. Any region of the substrate is pinned to itself. Further devices like A pmos and nmos would almost always have at least the channel pinned to the regions surrounding it. Since the channel is more often than not the same conductivity as a body it is formed in so it is pinned to the substrate. Thus, the scope of pinned area would encompass most semiconductor switch devices. This can be seen in Rhodes 20060131592 the channel area under the gate is pinned to substrate underneath. It is noted pinned must be broader than claims 7-10 which define the pinned area. However, a bulk substrate would read on a pinned area. Claim 5 is unclear claim 4 requires the non-pinned photodiode is formed on a second semiconductor substrate different from the first substrate however claim 5 requires wherein the non-pinned photodiode is hybridized to the first substrate, the first substrate being made of silicon which means it is not entirely formed in the second substrate as stated in claim 4. Further it is unclear what is meant by hybridized. As to claim 7, It is unclear how a n-type semiconductor in a the pt-type substrate constitutes a “pinned” area. Claim 8 clarifies the 112b of the pinned area for claims 1 and 7. However there is no recited first semiconductor region in claim 7 there is a first n-type semiconductor region. Further claim 8 does not clarify how it is pinned. Claim 8 should recite wherein a second P-type doped semiconductor region formed in the first substrate is interposed between a top face of the first substrate and the firs N-type t semiconductor region and electrically connected to the p-substrate As to claim 10 claim 10 fails to structurally relate the third region to the first region. Claim 11 clarifies this relationship. Claims 13 fails to interconnect the photosensitive area to the non-pinned diode or how the non-pinned photodiodes relate to the element of claim 13. Further there is not second substrate recited in claim 1. It appears applicant means first substrate since applicant stated the photo sensitive area is in the first substrate. As to claim 15 it is unclear if the transfer gate in claim 15 is the same or different than that of claim 13. As to claim 16 it is unclear and confusing how one could determine whether or not wherein the pinned area is not intended to be subjected to incident light radiation. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 12, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stevens 20100148320. a. As to claim 1,Stevens teaches An image sensor comprising a plurality of pixels (figure 4 items 400), each pixel including a non-pinned photodiode connected (figure 5 the item 500 in this instance 514 does not pin the surfaces to the bulk since the bulk is item 518) , by a connecting element (item 508 the transistor), to a pinned area formed in a first semiconductor substrate (item 510 it pins or electrically connects the element to 518). Stevens does not teach that 508 is metal however metal gates were known at the time of filing to provide lower resistance prevent depletion of the polysilicon gate. Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form the gates to use conventional gate materials to provide expected outcomes of higher conductivity and elimination of depletion of the poly silicon gate. b. As to claim 2 anode and cathode are intended use since Stevens teaches a p-type and p-type photodiode the claim is read on. c. As to claim 3, Stevens teaches wherein the anode and cathode semiconductor regions of the non-pinned photodiode are joined d. As to claim 12, Stevens wherein each pixel further includes a transistor connected between the metal connection element and the pinned area ( item 604). e. As to claim 16, Stevens teaches wherein the pinned area is not intended to be subjected to incident light radiation (it is not designed to directly receive light since it is not a photo diode). Claim Rejections - 35 USC § 103 Claim(s) 1-3, 7-9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee “Image Artifacts by Charge Pocket in Floating Diffusion Region on CMOS Image Sensors” a. As to claim 1, Lee teaches a image An image sensor comprising a plurality of pixels (Introduction section) each pixel including a non-pinned photodiode connected,(figure 1a the surface PD does not have a pinning layer so it is unpinned) by a connecting element (Gate of the transistor figure 1a), to a pinned area formed in a first semiconductor substrate (floating diffusion region is pinned to the substrate). Lee does not teach a metal connecting element/gate however metal gates were known at the time of filing to provide lower resistance prevent depletion of the polysilicon gate. Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form the gates to use conventional gate materials to provide expected outcomes of higher conductivity and elimination of depletion of the poly silicon gate. b. As to claim 2, Lee wherein the non-pinned photodiode comprises a P-type doped anode semiconductor region and an N-type doped cathode semiconductor region (figure 1a). c. As to claim 3, Lee teaches wherein the anode and cathode semiconductor regions of the non-pinned photodiode are joined (figure 1a). d. As to claim 7-8, Lee teaches wherein the pinned area comprises a first N-type doped semiconductor region formed in the first substrate, the first substrate being P-type doped (p-type substrate with n-type well and a p-type layer at the surface connected to the p-type substrate figure 1a). e. As to claim 9 Lee does not explicitly teach wherein the second semiconductor region has a higher doping level than the first substrate. However, such concentrations were known and the concentration would affect leakage. Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide wherein the second semiconductor region has a higher doping level than the first substrate. To optimize the reduction in leakage. f. As to claim 16, Lee teaches wherein the pinned area is not intended to be subjected to incident light radiation (it is a floating diffusion region). Allowable Subject Matter Claim 4-6- 10-11 and 13-15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F. Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW L. REAMES/ Primary Examiner Art Unit 2896 /MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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Prosecution Timeline

Aug 12, 2024
Application Filed
Aug 05, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
95%
With Interview (+18.0%)
2y 8m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1101 resolved cases by this examiner. Grant probability derived from career allowance rate.

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