DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 6-8 ,14, 16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 9-10,15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee at al. (Pub No. US 2022012750) in view of Satyamsetti (Pub No. US 2024/0134986)
Regrading Claim 1 Lee teaches: an interface [Fig.4, CPU corresponds to interface, [0122] the processor may interface with the RoT module 420 through a high-speed JO bus] provided on at least one circuit to initiate fetches that are loaded to a Root of Trust (RoT) module [[0129] [0132] RoT module verifies the integrity of the first boot firmware by reading from the first boot memory] and to enforce a boot policy [Fig.6, item 640 and 650, Release or reset corresponds to boot policy] that requires acknowledgement [[Fig.6, item 630, [0132] RoT module verifies the integrity of the first boot firmware by reading from the first boot memory (existence of integrity in the firmware )] and approval [Fig.6, item 635, Has verification succeeded] of at least a system-on-chip (SoC) [[0195] [0147] RoT module according to an embodiment of the present invention may be a semiconductor chip in the form of an SoC that supports a secure boot function ]] manager and the RoT module to continue a boot process. [Fig.6, item 640, [0136] the boot control circuit checks at step S635 whether integrity verification succeeds. When integrity verification succeeds, the boot control circuit releases the reset state of the processor and sets the route of the boot memory bus such that the processor is connected with the first boot memory, thereby controlling the processor so as to be booted normally]
Regrading Claim 1 Lee does not teach First Mutable Code (FMC)
However, Satyamsetti taches First Mutable Code (FMC) [[0034] RoT device 320 boots the First Mutable Code (FMC) provided by a manufacturer of the device]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention verify the First Mutable Code (FMC) in Lee’s system before Continuing boot process.
A person with Ordinary skill in the art would have been motivated to verify the First Mutable Code (FMC) in order to improve security, integrity, and operational control.
Regrading Claim 2 Lee teaches: the interface is comprised in a fixed-function hardware state machine or processor of the at least one circuit that is independent of further circuits comprising a plurality of processors associated with one [Fig.4, CPU of device 400, Device 400 is independent of network device, graphic device and I/O device] or more of the SoC manager or the RoT module.
Regrading Claim 9 Lee teaches: a system comprising: a system-on-chip (SoC) manager, [[0195] [0147] RoT module according to an embodiment of the present invention may be a semiconductor chip in the form of an SoC that supports a secure boot function ] a root of trust (RoT) module, [[0129] [0132] RoT module verifies the integrity of the first boot firmware by reading from the first boot memory] and an interface associated therewith, [Fig.4, CPU corresponds to interface, [0122] the processor may interface with the RoT module 420 through a high-speed JO bus] wherein the interface[Fig.4, CPU] is to receive boot media parameters [boot firmware] of connected and expected devices in the system, [[0065] designed their devices to verify first boot firmware by connecting with a hardware RoT module located inside or outside the devices,] to initiate fetches that are loaded to the RoT module, [[0129] [0132] RoT module verifies the integrity of the first boot firmware by reading from the first boot memory] and to enforce a boot policy [Fig.6, item 640 and 650, Release or reset corresponds to boot policy] that requires acknowledgement [[Fig.6, item 630, [0132] RoT module verifies the integrity of the first boot firmware by reading from the first boot memory (existence of integrity in the firmware )] and approval [[Fig.6, item 635, Has verification succeeded]] of at least the SoC manager and the RoT module to continue a boot process. [Fig.6, item 640, [0136] the boot control circuit checks at step S635 whether integrity verification succeeds. When integrity verification succeeds, the boot control circuit releases the reset state of the processor and sets the route of the boot memory bus such that the processor is connected with the first boot memory, thereby controlling the processor so as to be booted normally]
Regrading Claim 9 Lee does not teach First Mutable Code (FMC).
However, Satyamsetti taches First Mutable Code (FMC) [[0034] RoT device 320 boots the first mutable code provided by a manufacturer of the device]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention verify the First Mutable Code (FMC) in Lee’s system before Continuing boot process.
A person with Ordinary skill in the art would have been motivated to verify the First Mutable Code (FMC) in order to improve security, integrity, and operational control.
Regrading Claim 10 Lee teaches: the interface is comprised in a fixed-function hardware state machine or processor of the plurality of circuits, [Fig.4, CPU of device 400, Device 400 is independent of network device, graphic device and I/O device] and wherein the plurality of circuits comprise independent processors associated with one or more of the SoC manager or the RoT module.
Claim 15 is having similar limitations to that of the apparatus of claim 1.Accordingly, claim 15 is rejected under a similar rational as that of claim 1 above.
Claim 18 is having similar limitations to that of the apparatus of claim 9.Accordingly, claim 15 is rejected under a similar rational as that of claim 9 above.
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee at al. (Pub No. US 2022012750) in view of Satyamsetti (Pub No. US 2024/0134986) further in view of Chu (Pub No. US 2024/02117272)
Regrading Claim 3 the combination of Lee and Satyamsetti does not teach: a reporting feature to sign measurements associated with an attester's configuration, a storage feature to hold the measurements, and an identity feature to issue and endorse identifies of an attester in the system.
However, Chu teaches a reporting feature to sign measurements associated with an attester's configuration, [[0062] first security signature generated from the device SK of the device ID key pair. For example, the attester FW 130 may generate the first security signature, which is a basis for generating a device certificate, based on the device SK] a storage feature to hold the measurements, [[0065] The code information register 141a according to some example embodiments may store information on a measurement value of a device configuration. For example, the code information register 141a may store first information that is a reference of measurement values of the device identification module 110, second information that is a reference of measurement values of the bootloader 120, and/or third information that is a reference of measurement values of the attester FW 130. ] and an identity feature to issue and endorse identifies of an attester in the system. [[0071] [0079] he device identification module 110 matches the preset (or alternately given) first information (S530) [0080] When it is determined that the first measurement value MR of the device identification module 110 matches the preset (or alternately given) first information, the device 100 according to some example embodiments may store the first measurement value MR. For example, the device 100 may measure the first measurement value MR of the device identification module 110]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to sign and store the measurement and identity the features to issue and endorse identifies of an attester in the system in Lee’s system using Chu’s teaching .
A person with ordinary skill in the art would have been motivated to combine Lee Satyamsetti and Chu to improve system’s trustworthiness and prevent unauthorized access.
Claim 11 is having similar limitations to that of the apparatus of claim 3.Accordingly, claim 11 is rejected under a similar rational as that of claim 3 above.
Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee at al. (Pub No. US 2022012750) in view of Satyamsetti (Pub No. US 2024/0134986) further in view of Mehta et al. (Pub No. US 2017/0140146)
Regarding Claim 4 the combination of Lee and Satyamsetti does not teach the boot media parameters are determined based in part on detected ones of the connected and the expected devices from a recovery mode select feature of the system.
However, Mehta teaches the boot media parameters are determined based in part on detected ones of the connected and the expected devices from a recovery mode select feature of the system. [[0073] consumer device(s) 102 are in a recovery mode and various functionalities are not accessible (such as the Operating System), an FFU tool can be used to flash an image to firmware of consumer device(s) 102. Basic Input/Output System (BIOS) which can define system and/or boot parameters of consumer device(s) 102]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to define the boot parameter in Lee’s system using Mehta’s teaching
A person with ordinary skill in the art would have been motivated to combine Lee Satyamsetti and Metha to have precise control over the operating system's startup process, hardware initialization, and troubleshooting.
Claim 12 is having similar limitations to that of the apparatus of claim 4.Accordingly, claim 12 is rejected under a similar rational as that of claim 4 above.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee at al. (Pub No. US 2022012750) in view of Satyamsetti (Pub No. US 2024/0134986) further in view of Kim (Pub No.US 2019/0051371)
Regarding Claim 5 the combination of Lee and Satyamsetti does not teach at least a clock to be associated with the interface is determined, in part, from the boot media parameters and using a fuse hardware feature of the system.
However, Kim teaches at least a clock to be associated with the interface is determined, in part, from the boot media parameters and using a fuse hardware feature of the system. [[0073 ] The fuse controller 110 may generate a clock signal CLK periodically enabled when the boot-up signal BOOTUP is enabled. If the number of fuses is 20, the 20 fuses F0 to F19 may correspond to a particular logic level (e.g., a logic high level as shown in FIG. 5) of the clock signal CLK.]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use the fuse control to generate clock signal for the processor in Lee’s system.
A person with ordinary skill in the art would have been motivated to combine Lee, Satyamsetti and Kim to improve system productivity in Lee’s system. [0006]
Claim 13 is having similar limitations to that of the apparatus of claim 5.Accordingly, claim 13 is rejected under a similar rational as that of claim 5 above.
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee at al. (Pub No. US 2022012750) in view of Satyamsetti (Pub No. US 2024/0134986) further in view of Righi et al. (Righi) (Patent NO. US 11,847,226)
Regarding Claim 17 the combination of Lee and Satyamsetti does not teach the at least one circuit is further to: allow the SoC manager to copy the firmware to a storage of the SoC manager, wherein the firmware enables the SoC manager to continue the boot process.
However, Righi teaches the at least one circuit is further to: allow the SoC manager to copy the firmware to a storage of the SoC manager, [col.7, lines 29-35, the security processor 130 might retrieve a valid copy of the firmware 140 for the BMC SOC 120 and store the firmware 140 in the memory device 108A .] wherein the firmware enables the SoC manager to continue the boot process. [col.9 27-32, where the security processor 130 enables the host processor 104 to exit from reset and to begin executing the host firmware 142]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to store and boot firmware in Lee’s system using Righi teaching.
A person with ordinary skill in the art would have been motivated to combine Lee, Satyamsetti and Kim to reduce boot time and improve system stability.
Claim 20 is having similar limitations to that of the apparatus of claim 17.Accordingly, claim 20 is rejected under a similar rational as that of claim 17 above.
Conclusion
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/ZAHID CHOUDHURY/Primary Examiner, Art Unit 2175