DETAILED ACTION
This Office Action is in response to an application that was filed on 08/12/2024. Claims 1-20 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 3, 6, 7, 8, 9, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hattori et a. (US20140041914A1 and Hattori hereinafter), in view of Yamamoto et al. (US20120236461A1 and Yamamoto hereinafter).
Regarding claim 1, Hattori discloses a mounting structure (Figs. 1A-2A and ¶[0027-0028_0035_0040 & 0042] shows and indicates mounting structure of Figs. 1A-2A) comprising a multilayer ceramic electronic component mounted on a circuit board (items 5, 100 of Figs. 1A-1B & item 5 of Fig. 2A and ¶[0036-0038 & 0040-0043] shows and indicates multilayer ceramic electronic component 5 {laminated ceramic capacitor 5} mounted on circuit board 100 {substrate 100}), the multilayer ceramic electronic component including a multilayer body including a plurality of dielectric layers including ceramic material and a plurality of inner conductive layers stacked on each other (item 50 of Figs. 1B-2A & item 5 of Fig. 2A & Fig. 1A and ¶[0036-0038 & 0040-0044] shows and indicates multilayer ceramic electronic component 5 including multilayer body 50 {laminate 50} including a plurality of dielectric layers 50-layers {ceramic layers that forms laminate 50} including ceramic material and a plurality inner conductive layers 55 {inner electrodes 55} stacked on each other), the multilayer body including two main surfaces on opposite sides in a thickness direction, two lateral surfaces on opposite sides in a width direction intersecting with the thickness direction, and two end surfaces on opposite sides in a length direction intersecting with both the thickness direction and the width direction (items W, L of Fig. 1A & items H, W, L of Fig. 1B-2A and ¶[0042-0044_0047-0049 & 0050] shows and indicates multilayer body 50 including two main surfaces 50-H {two opposing surfaces in height direction H of laminate 50} on opposite sides in thickness direction H {height direction H}, two lateral surfaces 50-W {two opposing surfaces in width direction W of laminate 50} on opposite sides in width direction W intersecting with thickness direction H, and two end surfaces 50-L {two opposing surfaces in length direction L of laminate 50} on opposite sides in length direction L intersecting with both thickness direction H and width direction W); and first and second external electrodes spaced apart in the length direction, provided on the two main surfaces of the multilayer body (items 51, 52 of Figs. 1A-2A and ¶[0044-0046] shows and indicates first and second external electrodes 51 & 52 {outer electrode 51 and outer electrode 52} spaced apart in length direction L, provided on the two main surfaces 50-H of multilayer body 50); wherein the circuit board includes a first land electrode and a second land electrode that are spaced apart in the length direction, and are respectively connected to the first external electrode and the second external electrode of the multilayer ceramic electronic component (items 10, 20 of Fig. 1A & 1B and ¶[0046-0047] shows and indicates where circuit board 100 includes first land electrode 10 {land pattern 10} and second land electrode 20 {land pattern 20} that are spaced apart in length direction L; and where first land electrode 10 is connected to first external electrode 51 of multilayer ceramic electronic component 5; and where second land electrode 20 is connected to second external electrode 52 of multilayer ceramic electronic component 5); an inner edge of the first external electrode on a second external electrode side in the length direction is located closer to the second external electrode side and a second land electrode side, than an inner edge of the first land electrode on the second land electrode side in the length direction; and an inner edge of the second external electrode on a first external electrode side in the length direction is located closer to the first external electrode side and a first land electrode side, than an inner edge of the second land electrode on the first land electrode side in the length direction (Figs. 1A-1B and ¶[0044-0047] shows where the inner edge of first external electrode 51 on second external electrode 52 side in length direction L is located closer to second external electrode 52 side and second land electrode 20 side, than the inner edge of first land electrode 10 on second land electrode 20 side in length direction L; and where the inner edge of second external electrode 52 on first external electrode 51 side in length direction L is located closer to first external electrode 51 side and first land electrode 10 side, than the inner edge of second land electrode 20 on first land electrode 10 side in length direction L).
Hattori discloses the claimed invention except to explicitly disclose wherein first and second external electrodes spaced apart in the length direction, provided on only the two main surfaces of the multilayer body or only one of the two main surfaces of the multilayer body.
Yamamoto discloses wherein first and second external electrodes spaced apart in the length direction, provided on only the two main surfaces of the multilayer body or only one of the two main surfaces of the multilayer body (items 13, 14, 10, L of Figs. 6-11 & items 10a, 10b of Figs. 6-11 & item 2 of Figs. 6-8 & item 3 of Figs. 9-11 and ¶[0035-0038_0042_0067_0073-0075] shows and indicates where first and second external electrodes 13 & 14 spaced apart in length direction L that is provided on only two main surfaces 10a & 10b of multilayer body 10 {ceramic element assembly 10} in multilayer ceramic electronic component 2; or where first and second external electrodes 13 & 14 spaced apart in length direction L that is provided on only one of the two main surfaces 10b of multilayer body 10 in multilayer ceramic electronic component 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein first and second external electrodes spaced apart in the length direction, provided on only the two main surfaces of the multilayer body or only one of the two main surfaces of the multilayer body into the structure of Hattori. One would have been motivated in the mounting structure of Hattori and have the first and second external electrodes be spaced apart in the length direction and be provided on only the two main surfaces of the multilayer body or on only one of the two main surfaces of the multilayer body, in order to design a mounting structure for a multilayer ceramic electronic component that significantly has reduced the surface area of the first and second external electrodes, as shown by Yamamoto in Figs. 6-11, from Hattori’s first and second external electrodes so as to reduce the possibility of plating film detachment from the external electrodes, as inferred by Yamamoto in ¶[0006], in the mounting structure of Hattori.
Regarding claim 2, modified Hattori discloses a mounting structure, wherein an outer edge of the first external electrode on a side opposite to the inner edge of the first external electrode in the length direction is located closer to the second external electrode side and the second land electrode side, than an outer edge of the first land electrode on a side opposite to the inner edge of the first land electrode in the length direction; and an outer edge of the second external electrode on a side opposite to the inner edge of the second external electrode in the length direction is located closer to the first external electrode side and the first land electrode side, than an outer edge of the second land electrode on a side opposite to the inner edge of the second land electrode in the length direction (Hattori: Figs. 1A-1B and ¶[0044-0047] shows where the outer edge of first external electrode 51 on the side opposite to the inner edge of first external electrode 51 in length direction L is located closer to second external electrode 52 side and second land electrode 20 side, than the two smaller side outer edges of first land electrode 10 on a side opposite to the inner edge of first land electrode 10 in length direction L; and where the outer edge of second external electrode 52 on the side opposite to the inner edge of second external electrode 52 in length direction L is located closer to first external electrode 51 side and first land electrode 10, than the two smaller side outer edges of second land electrode 20 on the side opposite to the inner edge of second land electrode 20 in length direction L).
Regarding claim 3, modified Hattori discloses a mounting structure, wherein a distance between the inner edge of the first external electrode and the inner edge of the second external electrode is shorter than a distance between the inner edge of the first land electrode and the inner edge of the second land electrode (Hattori: Figs. 1A-1B and ¶[0044-0047] shows where the distance between the inner edge of first external electrode 51 and the inner edge of second external electrode 52 is shorter than the distance between the inner edge of first land electrode 10 and the inner edge of second land electrode 20).
Regarding claim 6, modified Hattori discloses a mounting structure, wherein the multilayer ceramic electronic component is a multilayer ceramic capacitor (Yamamoto: Figs. 9-11 and ¶[0033] indicates where multilayer ceramic electronic component 2/3 is a multilayer ceramic capacitor).
Regarding claim 7, modified Hattori discloses a mounting structure, wherein the multilayer ceramic electronic component is a piezoelectric component (Yamamoto: Figs. 9-11 and ¶[0034] indicates where multilayer ceramic electronic component 2/3 is a piezoelectric component).
Regarding claim 8, modified Hattori discloses a mounting structure, wherein the multilayer ceramic electronic component is a thermistor (Yamamoto: Figs. 9-11 and ¶[0035] indicates where multilayer ceramic electronic component 2/3 is a thermistor).
Regarding claim 9, modified Hattori discloses a mounting structure, wherein the multilayer ceramic electronic component is an inductor (Yamamoto: Figs. 9-11 and ¶[0036] indicates where multilayer ceramic electronic component 2/3 is an inductor).
Regarding claim 10, modified Hattori discloses a mounting structure, wherein the multilayer ceramic electronic component includes piezoelectric ceramics, semiconductor ceramics, or magnetic ceramics (Yamamoto: Figs. 9-11 and ¶[0034-0036] indicates where multilayer ceramic electronic component 2/3 includes piezoelectric ceramics, semiconductor ceramics, or magnetic ceramics).
Regarding claim 11, modified Hattori discloses a mounting structure, wherein each of the first and second external electrodes includes only a plated layer (Hattori: Figs. 1A-2A and ¶[0045] indicates where each of first and second external electrodes 51 & 52 includes only a plated layer).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hattori in view of Yamamoto, as detailed in the rejection of claim 1, and in further view of NPL “IPC-SM-782 Land Dimension Standards_pages 1-122_Aug 1993” (NPL “IPC-SM-782” hereinafter).
Regarding claim 4, modified Hattori discloses a mounting structure, wherein a dimension of each of the first and second external electrodes in the length direction is about 74% or more of a dimension of each of the first and second land electrodes in the length direction (Hattori: Fig. 1A and ¶[0044-0047] is broadly interpreted by extrapolation to show where the dimension of each of first and second external electrodes 51 & 52 in length direction L is about 50% or more of the dimension of each of the first and second land electrodes 10 & 20 in length direction L).
However, Hattori and Yamamoto do not explicitly disclose wherein a dimension of external electrodes in the length direction is about 74% or more of a dimension of the land electrodes in the length direction.
NPL “IPC-SM-782” discloses wherein a dimension of external electrodes in the length direction is about 74% or more of a dimension of the land electrodes in the length direction (pages 7 to 10 under “Chip Capacitors” shows and indicates where the dimension of the external electrodes in the length direction would be about 74% or more of the dimension of the land electrodes in the length direction using the Tables in the Figures. Therefore, based on the following criteria, the 74% tolerance can closely be obtained: Ceramic Chip Component Dimensional Identifier Table of Fig. 2; Land Pattern Dimensional Table of Fig. 3; and Solder Joint Table of Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein a dimension of external electrodes in the length direction is about 74% or more of a dimension of the land electrodes in the length direction into the structure of modified Hattori. One would have been motivated in the mounting structure of Hattori and have the dimension of the external electrodes in the length direction be about 74% or more of the dimension of the land electrodes in the length direction, in order to design a mounting structure by complying by the “Surface Mount Design and Land Pattern Standard” of IPC-SM-782, as shown and indicated by NPL “IPC-SM-782” under Chip Capacitors, in the mounting structure of modified Hattori.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hattori in view of Yamamoto, as detailed in the rejection of claim 1, and in further view of Hirukawa et al. (US20220262559A1 and Hirukawa hereinafter).
Regarding claim 5, modified Hattori discloses a mounting structure, wherein a dimension of each of the first and second external electrodes in the width direction (Hattori: Fig. 1A and ¶[0044-0046] shows where the dimension of each of the first and second external electrodes 51 & 52 has a width direction W dimension).
However, Hattori and Yamamoto do not disclose wherein a dimension of external electrodes in the width direction is between about 0.12 mm and about 0.21 mm inclusive.
Hirukawa discloses wherein a dimension of external electrodes in the width direction is between about 0.12 mm and about 0.21 mm inclusive (items 21, 22, W1, 1 of Fig. 3 and ¶[0069_0073 & 0075] shows and indicates where the dimension of external electrodes 21 & 22 in the width direction is between about 0.12 mm and about 0.21 mm inclusive {dimension W1 of the multilayer coil component 1 in the width direction W is 0.18 mm or more to width direction W is 0.22 mm or less}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein a dimension of external electrodes in the width direction is between about 0.12 mm and about 0.21 mm inclusive into the structure of modified Hattori. One would have been motivated in the mounting structure of Hattori and have the dimension of external electrodes in the width direction is between about 0.12 mm and about 0.21 mm inclusive, in order to design a mounting structure by complying to the appropriate size external electrodes, as indicated by Hirukawa in ¶[0066], in the mounting structure of modified Hattori.
Claims 12, 13, 14, 15, 16, 17, 18, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hattori in view of Yamamoto, as detailed in the rejection of claim 1, and in further view of Togo (US20220068562A1 and Togo hereinafter).
Regarding claim 12, modified Hattori discloses a mounting structure, wherein each of the first and second external electrodes includes a base electrode layer and a plated layer (Yamamoto: items 13a, 13b, 13c, 14a, 14b, 14c of Fig. 2 & items 13a, 13b, 13c of Fig. 3 & items 14a, 14b, 14c of Fig. 4 and ¶[0055] is interpreted to show and indicate where first external electrodes 13 includes base electrode layer 13a {plating film 13a} and plated layer 13b_13c {plating films 13b and 13c}; and where second external electrodes 14 includes base electrode layer 14a {plating film 14a} and plated layer 14b_14c {plating films 14b and 14c}).
However, Hattori and Yamamoto do not explicitly disclose wherein each of the first and second external electrodes includes a base electrode layer and a plated layer.
Togo discloses wherein each of the first and second external electrodes includes a base electrode layer and a plated layer (items 30a, 30b, 32, 34 of Fig. 5 and ¶[0067-0068_0070 & 0088-0091] shows and indicates where each of first and second external electrodes 30a & 30b {first outer electrode 30a and second outer electrode 30b} includes base electrode layer 32 and plated layer 34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein each of the first and second external electrodes includes a base electrode layer and a plated layer into the structure of modified Hattori. One would have been motivated in the mounting structure of Hattori and have each of the first and second external electrodes include a base electrode layer and a plated layer, in order to design a mounting structure that will increase the functionality of the multilayer ceramic electronic component by enhancing the electrical connectivity between the inner conductive layers internal to the component to the external electrodes of the component, as indicated by Togo in ¶[0008], in the mounting structure of modified Hattori.
Regarding claim 13, modified Hattori discloses a mounting structure, wherein the base electrode layer includes metal (Togo: Fig. 5 and ¶[0068_0070 & 0073] shows and indicates where base electrode layer 32 is a fired layer {baked} including metal and glass).
Regarding claim 14, modified Hattori discloses a mounting structure, wherein the base electrode layer is a resin layer including electrically conductive particles and a thermosetting resin (Togo: Fig. 5 and ¶[0081 & 0083] shows and indicates where base electrode layer 32 is a resin layer including electrically conductive particles and a thermosetting resin).
Regarding claim 15, modified Hattori discloses a mounting structure, wherein a thickness of the base electrode layer and a thickness of the plated layer is about 1 μm and about 10 μm inclusive (Togo: Fig. 5 and ¶[0091] shows and indicates where the thickness of plated layer 34 is about 1 μm and about 10 μm inclusive; Fig. 5 and ¶[0081-0082] is interpreted to indicate where the thickness of base electrode layer 32 is about 1 μm and about 10 μm inclusive {based on having an average particle size of the conductive filler that may be from 0.3 μm to 10 μm that would then constitute the thickness}).
Regarding claim 16, modified Hattori discloses a mounting structure, wherein the base electrode layer includes a thin film layer of metal particles deposited to a thickness of about 1 μm or less (Togo: Fig. 5 and ¶[0081-0082] is interpreted to indicate where base electrode layer 32 includes a thin film layer of metal particles deposited to a thickness of about 1 μm or less {based on having a film of an average particle size of the conductive filler that may be from 0.3 μm to 10 μm, and having the metal be included in the conductive resin layer}).
Regarding claim 17, modified Hattori discloses a mounting structure, wherein the plated layer covers at least a portion of the base electrode layer (Togo: Fig. 5 and ¶[0067-0068_0070 & 0088-0091] shows and indicates where plated layer 34 covers base electrode layer 32).
Regarding claim 18, modified Hattori discloses a mounting structure, wherein the plated layer includes Cu, Ni, Ag, Pd, Au, or an alloy or an Ag—Pd alloy (Togo: Fig. 5 and ¶[0089] shows and indicates where plated layer 34 includes Cu, Ni, Ag, Pd, Au, or an alloy or an Ag—Pd alloy).
Regarding claim 19, modified Hattori discloses a mounting structure, wherein the plated layer includes a plurality of layers (Togo: Fig. 5 and ¶[0090-0091] shows and indicates where plated layer 34 includes a plurality of layers).
Regarding claim 20, modified Hattori discloses a mounting structure, wherein the plated layer includes a Ni plated layer and a Sn plated layer (Togo: Fig. 5 and ¶[0091] shows and indicates where plated layer 34 includes a Ni plated layer and a Sn plated layer).
Conclusion
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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