DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 9 and 16.
b. Pending: 1-20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-12, 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hyun PG PUB 20130205085 (hereinafter Hyun).
Regarding independent claim 1, Hyun teaches a memory device (104 in figure 1 of Hyun), comprising:
a memory array (126 in figure 2 of Hyun) comprising a plurality of memory cells electrically coupled to a plurality of conductive lines (WL /BL in figure 2 of Hyun); and
a controller (114 in figure 1 of Hyun) coupled to the memory array, the controller to perform operations comprising:
performing (502 in figure 5 of Hyun) a memory programming operation with respect to a set of memory cells of the memory array;
responsive to receiving a command to perform a memory access operation (504 in figure 5 of Hyun, [0038] of Hyun, “…in response to receiving a read access request…”), suspending the memory programming operation (yes branch after 506, 508 in figure 5 of Hyun);
resuming the memory programming operation (514 in figure 5 of Hyun, [0053], “…the controller 114 sends a resume command…”); and
performing the memory access operation (512 in figure 5 of Hyun) by storing one or more data items read from the memory array in an input/output (I/O) buffer (162 in figure 2 of Hyun, or 402 in figure 4A of Hyun) associated with the set of memory cells ([0051] of Hyun, “…memory control manager 140 may then perform the read operation at the memory elements 126 and retrieve the data stored at the specified address(es)…”, [0069] of Hyun, “…a read buffer 402 to store data read from the memory elements 126…”, buffers 400/402 are connected via sense amplifiers 146 to memory elements), wherein the I/O buffer is not utilized by the memory programming operation ([0051] of Hyun, “… the data being written to the memory elements 126 stored in the I/O buffer 148 is transferred to a cache buffer 162 for temporary storage while the program operation is suspended…”, [0069] of Hyun, “…In other embodiments…the memory device 116 includes a program buffer 400 to store data to be written to the memory elements 126 and a read buffer 402 to store data read from the memory elements 126. In such embodiments, the data corresponding to the program operation may be stored in the program buffer 400 and does not need to be transferred to another buffer. The program buffer 400 and the read buffer 402 may be connected to the same sense amplifier 146 or separate sense amplifiers 146 for transferring data between the buffers and the memory elements 126…”, therefore, during the read operation, the I/O buffer is not being used by the programming operation).
Regarding claim 2, Hyun teaches the memory device of claim 1, wherein programming operation data for the programming operation is stored in a page buffer associated with the set of memory cells (400 in figure 4A of Hyun).
Regarding claim 3, Hyun teaches the memory device of claim 1, wherein the I/O buffer is represented by a secondary data cache (SDC) associated with the set of memory cells (162 in figure 2 of Hyun, [0051] of Hyun, “…the data being written to the memory elements 126 stored in the I/O buffer 148 is transferred to a cache buffer 162 for temporary storage while the program operation is suspended…”).
Regarding claim 4, Hyun teaches the memory device of claim 1, wherein suspending the memory programming operation further comprises: storing, in a page buffer associated with the set of memory cells, a status of the programming operation ([0036] of Hyun, “…the program suspend module 120 is configured to store information that defines the state or progress of the program operation, including a pulse count at which the current program operation is suspended...”)
Regarding claim 5, Hyun teaches the memory device of claim 1, wherein the memory programming operation further comprises one or more program verify operations to compare threshold voltage levels of the set of memory cells to at least one predefined threshold voltage level ([0030] of Hyun, “…memory elements 126 may be programmed to different states depending on the desired bit configuration for each memory element 126...”, figure 3A/3B teaches an ISPP program method, [0054], “…the voltage pulses for a program operation may be performed using an ISPP approach…”).
Regarding claim 7, Hyun teaches the memory device of claim 1, wherein the memory access operation is a read operation ([0051] of Hyun, “…memory control manager 140 may then perform the read operation at the memory elements 126 and retrieve the data stored at the specified address(es)…”, [0038], “…read access request…”).
Regarding claim 8, Hyun teaches the memory device of claim 1, wherein the set of memory cells is a block of the memory array (126 in figure 2, NAND arrays organize in blocks).
Regarding independent claim 9, Hyun teaches a memory device, comprising:
a memory array (126 in figure 2 of Hyun) comprising a plurality of memory cells electrically coupled to a plurality of conductive lines (WL /BL in figure 2 of Hyun); and
a controller (114 in figure 1 of Hyun) coupled to the memory array, the controller to perform operations comprising:
performing a memory programming operation (502 in figure 5 of Hyun) with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a first sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells (figure 3A/3B teaches an ISPP program method, [0054], “…the voltage pulses for a program operation may be performed using an ISPP approach…”);
responsive to receiving a command to perform a memory access operation (504 in figure 5 of Hyun, [0038] of Hyun, “…in response to receiving a read access request…”), suspending the memory programming operation after performing a current programming pulse of the first sequence of programming pulses (yes branch after 506, 508 in figure 5 of Hyun);
resuming the memory programming operation (514 in figure 5 of Hyun, [0053], “…the controller 114 sends a resume command…”); and
completing the memory access operation (512 in figure 5 of Hyun) by storing one or more data items read from the memory array in a secondary data cache (SDC) associated with the set of memory cells (162 in figure 2 of Hyun, or 402 in figure 4A of Hyun) associated with the set of memory cells ([0051] of Hyun, “…memory control manager 140 may then perform the read operation at the memory elements 126 and retrieve the data stored at the specified address(es)…”, [0051] of Hyun, “…the data being written to the memory elements 126 stored in the I/O buffer 148 is transferred to a cache buffer 162 for temporary storage while the program operation is suspended…”, [0069] of Hyun, “…a read buffer 402 to store data read from the memory elements 126…”).
Regarding claim 10, Hyun teaches the memory device of claim 9, wherein programming operation data for the programming operation is stored in a page buffer associated with the set of memory cells (400 in figure 4A of Hyun).
Regarding claim 11, Hyun teaches the memory device of claim 9, wherein suspending the memory programming operation further comprises: storing, in a page buffer associated with the set of memory cells, a status of the programming operation ([0036] of Hyun, “…the program suspend module 120 is configured to store information that defines the state or progress of the program operation, including a pulse count at which the current program operation is suspended...”)
Regarding claim 12, Hyun teaches the memory device of claim 9, wherein the memory programming operation further comprises one or more program verify operations to compare threshold voltage levels of the set of memory cells to at least one predefined threshold voltage level ([0030] of Hyun, “…memory elements 126 may be programmed to different states depending on the desired bit configuration for each memory element 126...”, figure 3A/3B teaches an ISPP program method, [0054], “…the voltage pulses for a program operation may be performed using an ISPP approach…”).
Regarding claim 14, Hyun teaches the memory device of claim 9, wherein the memory access operation is a read operation ([0051] of Hyun, “…memory control manager 140 may then perform the read operation at the memory elements 126 and retrieve the data stored at the specified address(es)…”, [0038], “…read access request…”).
Regarding claim 15, Hyun teaches the memory device of claim 9, wherein the set of memory cells is a block of the memory array (126 in figure 2, NAND arrays organize in blocks).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 13, 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hyun PG PUB 20130205085 (hereinafter Hyun), in view of SHIBATA PG PUB 20070171721 (hereinafter SHIBATA).
Regarding claim 6, Hyun teaches the memory device of claim 1, but does not teach wherein performing the memory access operation is performed simultaneously with performing one or more programming pulses of the resumed memory programming operation.
However, Shibata teaches read during ongoing memory operation. Figure 11A/11B show suspend program and perform read operation, then resume program, and show overlapping pipeline behavior, cache is used during program, read insert into flow, and program continues using cached data. This suggests an interleaved/concurrent operation. Figure 14/14B teaches “read next page during data output”, indicates while output (ongoing operation), another read is executed. [0133] of Shibata teaches an overlapping operation ([0133], “…when DDC becomes available or immediately after the input of the read command, the write (program) operation is suspended and a read operation is performed. The read data is subsequently transferred to SDC and then output to the external device. During the output, the last write operation may be resumed...”)
Hyun teaches suspend, read and resume sequence. Shibata teaches an interleave/overlapping read and program, it would have been obvious to modify Hyun to use Shibata’s cache-based interleaving technique to allow read operations to occur concurrently with programming operations to improve performance.
Note: under BRI, “simultaneously” does not require that all portions of the read and program operations fully overlap in time. Rather, as illustrated in Applicant’s figure 5, and 6, “simultaneously” encompasses embodiments in which a read operation is initiated during a suspension period and continues into a period whether programming has resumed, such that both operations are occurring concurrently for at least a portion of time.
Regarding claim 13, the combination of Hyun and Shibata teaches the memory device of claim 9, wherein completing the memory access operation is performed simultaneously with performing one or more programming pulses of the resumed memory programming operation ([0133] of Shibata, “…when DDC becomes available or immediately after the input of the read command, the write (program) operation is suspended and a read operation is performed. The read data is subsequently transferred to SDC and then output to the external device. During the output, the last write operation may be resumed...”)
Regarding independent claim 16, the combination of Hyun and Shibata teaches a memory device, comprising:
a memory array (126 in figure 2 of Hyun) comprising a plurality of memory cells electrically coupled to a plurality of conductive lines (WL /BL in figure 2 of Hyun); and
a controller (114 in figure 1 of Hyun) coupled to the memory array, the controller to perform operations comprising:
performing a memory programming operation (502 in figure 5 of Hyun) with respect to a set of memory cells of the memory array, wherein the memory programming operation (502 in figure 5 of Hyun) comprises a first sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells (figure 3A/3B teaches an ISPP program method, [0054], “…the voltage pulses for a program operation may be performed using an ISPP approach…”);
responsive to receiving a command (504 in figure 5 of Hyun, [0038] of Hyun, “…in response to receiving a read access request…”) to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the first sequence of programming pulses (yes branch after 506, 508 in figure 5 of Hyun), wherein the current programming pulse is performed at a first voltage level;
completing (512 in figure 5 of Hyun), simultaneously with performing one or more programming pulses of the memory programming operation ([0133] of Shibata, “…when DDC becomes available or immediately after the input of the read command, the write (program) operation is suspended and a read operation is performed. The read data is subsequently transferred to SDC and then output to the external device. During the output, the last write operation may be resumed...”), the memory access operation by storing one or more data items read from the memory array in an input/output (I/O) buffer (402 in figure 4A of Hyun, [0069] of Hyun, “…In other embodiments…the memory device 116 includes a program buffer 400 to store data to be written to the memory elements 126 and a read buffer 402 to store data read from the memory elements 126. In such embodiments, the data corresponding to the program operation may be stored in the program buffer 400 and does not need to be transferred to another buffer. The program buffer 400 and the read buffer 402 may be connected to the same sense amplifier 146 or separate sense amplifiers 146 for transferring data between the buffers and the memory elements 126…”) associated with the set of memory cells, wherein the I/O buffer is not utilized by the memory programming operation.
Regarding claim 17, the combination of Hyun and Shibata teaches the memory device of claim 16, wherein programming operation data for the programming operation is stored in a page buffer associated with the set of memory cells (402 in figure 4A of Hyun, [0069] of Hyun, “…In other embodiments…the memory device 116 includes a program buffer 400 to store data to be written to the memory elements 126 and a read buffer 402 to store data read from the memory elements 126. In such embodiments, the data corresponding to the program operation may be stored in the program buffer 400 and does not need to be transferred to another buffer. The program buffer 400 and the read buffer 402 may be connected to the same sense amplifier 146 or separate sense amplifiers 146 for transferring data between the buffers and the memory elements 126…”).
Regarding claim 18, the combination of Hyun and Shibata teaches the memory device of claim 16, wherein the I/O buffer is represented by a secondary data cache (SDC) associated with the set of memory cells (162 in figure 2 of Hyun, or 402 in figure 4A of Hyun, [0051] of Hyun, “…the I/O buffer 148 is used for performing both program operations and read operations... the data being written to the memory elements 126 stored in the I/O buffer 148 is transferred to a cache buffer 162 for temporary storage while the program operation is suspended…”, [0069] of Hyun, “…In other embodiments…the memory device 116 includes a program buffer 400 to store data to be written to the memory elements 126 and a read buffer 402 to store data read from the memory elements 126. In such embodiments, the data corresponding to the program operation may be stored in the program buffer 400 and does not need to be transferred to another buffer. The program buffer 400 and the read buffer 402 may be connected to the same sense amplifier 146 or separate sense amplifiers 146 for transferring data between the buffers and the memory elements 126…”)
Regarding claim 19, the combination of Hyun and Shibata teaches the memory device of claim 16, wherein suspending the memory programming operation further comprises: storing, in a page buffer associated with the set of memory cells, a status of the programming operation ([0036] of Hyun, “…the program suspend module 120 is configured to store information that defines the state or progress of the program operation, including a pulse count at which the current program operation is suspended...”)
Regarding claim 20, the combination of Hyun and Shibata teaches the memory device of claim 16, wherein the memory programming operation further comprises one or more program verify operations to compare threshold voltage levels of the set of memory cells to at least one predefined threshold voltage level ([0030] of Hyun, “…memory elements 126 may be programmed to different states depending on the desired bit configuration for each memory element 126...”, figure 3A/3B teaches an ISPP program method, [0054], “…the voltage pulses for a program operation may be performed using an ISPP approach…”).
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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