Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 7/6/2026. The changes and remarks disclosed therein have been considered. Claims 1, 9, 16 have been amended. Therefore, claims 1-20 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hyun PG PUB 20130205085 (hereinafter Hyun), in view of SHIBATA PG PUB 20070171721 (hereinafter SHIBATA).
Regarding independent claim 1, Hyun teaches a memory device (104 in figure 1 of Hyun), comprising:
a memory array (126 in figure 2 of Hyun) comprising a plurality of memory cells electrically coupled to a plurality of conductive lines (WL /BL in figure 2 of Hyun); and
a controller (114 in figure 1 of Hyun) coupled to the memory array, the controller to perform operations comprising:
performing (502 in figure 5 of Hyun) a memory programming operation with respect to a set of memory cells of the memory array;
responsive to receiving a command to perform a memory access operation (504 in figure 5 of Hyun, [0038] of Hyun, “…in response to receiving a read access request…”), suspending the memory programming operation (yes branch after 506, 508 in figure 5 of Hyun);
resuming the memory programming operation (514 in figure 5 of Hyun, [0053], “…the controller 114 sends a resume command…”); and
performing the memory access operation (512 in figure 5 of Hyun) by storing one or more data items read from the memory array in an input/output (I/O) buffer (402 in figure 4A of Hyun) associated with the set of memory cells ([0051] of Hyun, “…memory control manager 140 may then perform the read operation at the memory elements 126 and retrieve the data stored at the specified address(es)…”, [0069] of Hyun, “…a read buffer 402 to store data read from the memory elements 126…”, buffers 400/402 are connected via sense amplifiers 146 to memory elements), wherein the I/O buffer is not utilized by the memory programming operation ( [0069] of Hyun, “…In other embodiments…the memory device 116 includes a program buffer 400 to store data to be written to the memory elements 126 and a read buffer 402 to store data read from the memory elements 126. In such embodiments, the data corresponding to the program operation may be stored in the program buffer 400 and does not need to be transferred to another buffer. The program buffer 400 and the read buffer 402 may be connected to the same sense amplifier 146 or separate sense amplifiers 146 for transferring data between the buffers and the memory elements 126…”, therefore, during the read operation, the I/O buffer is not being used by the programming operation).
Hyun teaches resuming the suspended programming operations. However Hyun teaches controller 114 issuing a resume command and therefore does not expressly teaches: “automatically resuming the memory programming operation upon initiating the memory access operation and without an externally-initiated resume command”.
Shibata teaches the missing limitation. Shibata teaches a NAND memory device in which an ongoing programming operation is interrupted in response to a read-command sequence. As shown in figure 11A and 11B, the externally supplied sequence 00h-Address-30h initiates the read operation. The device therefore performs the following internally controlled sequence: “suspend program and perform read operation” followed by “resume program”. No separate externally supplied resume command is shown between initiation of the read operation and resumption of programming. Shibata therefore teaches or at least suggest that resumption is internally controlled as part of the sequence initiated by the read command.
Shibata teaches in [0128] that after the read-start command 30h is accepted, the write operation is suspended, a read operation is performed, the read result is held in SDC or SDC/DDC, and the previous write operation is resumed during output of the read result. [0131] more specifically teaches that after receipt of read-start command 30h, the write operation is suspended, the read operation is performed, the read data is transferred to SDC and output, and “during the output to the external device, the last write operation is then resumed”. Thus Shibata teaches or at least suggests that initiation of the memory-access operation triggers an internally controlled suspend/read/resume sequence in which programming is automatically resumed without receipt of a separately externally initiated resume command.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Hyun’s suspend/read/resume procedure in accordance with Shibata so that, after initiation of an intervening read operation, the memory -device controller automatically resumes the suspended programming operation without requiring a separate externally supplied resume command. Such a modification would have reduced external command overhead and programming latency, while permitting programming to continue during remaining read-data transfer or output operations, thereby improving memory throughput.
Regarding claim 2, the combination of Hyun and Shibata teaches the memory device of claim 1, wherein programming operation data for the programming operation is stored in a page buffer associated with the set of memory cells (400 in figure 4A of Hyun).
Regarding claim 3, the combination of Hyun and Shibata teaches the memory device of claim 1, wherein the I/O buffer is represented by a secondary data cache (SDC) associated with the set of memory cells (SDC in [0128] of Shibata).
Regarding claim 4, the combination of Hyun and Shibata teaches the memory device of claim 1, wherein suspending the memory programming operation further comprises: storing, in a page buffer associated with the set of memory cells, a status of the programming operation ([0036] of Hyun, “…the program suspend module 120 is configured to store information that defines the state or progress of the program operation, including a pulse count at which the current program operation is suspended...”, [0037], [0068]-[0069] of Hyun, Hyun teaches that programming-state information, including pulse count, pulse amplitude, pulse duration and current voltage level, may be stored for resuming programming ([0036]/[0057]). Hyun further teaches that information describing progress of the programming operation may be stored in a buffer ([0068]), and identifies program buffer 400 as storing data to be written to memory elements 126 ([0069], figure 4A-4B). Thus Hyun teaches or suggest storing the status of the programming operation in program/page buffer 400 associated with the set of memory cells).
Regarding claim 5, the combination of Hyun and Shibata teaches the memory device of claim 1, wherein the memory programming operation further comprises one or more program verify operations to compare threshold voltage levels of the set of memory cells to at least one predefined threshold voltage level ([0030] of Hyun, “…memory elements 126 may be programmed to different states depending on the desired bit configuration for each memory element 126...”, figure 3A/3B of Hyun teaches an ISPP program method, [0054], “…the voltage pulses for a program operation may be performed using an ISPP approach…”, figure 10 of Shibata teaches program-verify operations using predetermined verify voltages a, b, c to determine whether the threshold voltage of a programed memory cell has reached the applicable verify level).
Regarding claim 6, the combination of Hyun and Shibata teaches the memory device of claim 1, wherein performing the memory access operation is performed simultaneously with performing one or more programming pulses of the resumed memory programming operation. (Shibata teaches read during ongoing memory operation. Figure 11A/11B of Shibata show suspend program and perform read operation, then resume program, and show overlapping pipeline behavior, cache is used during program, read insert into flow, and program continues using cached data. This suggests an interleaved/concurrent operation. Figure 14/14B of Shibata teaches “read next page during data output”, indicates while output (ongoing operation), another read is executed. [0133] of Shibata teaches an overlapping operation, “…when DDC becomes available or immediately after the input of the read command, the write (program) operation is suspended and a read operation is performed. The read data is subsequently transferred to SDC and then output to the external device. During the output, the last write operation may be resumed...”)
Note: under BRI, “simultaneously” does not require that all portions of the read and program operations fully overlap in time. Rather, as illustrated in Applicant’s figure 5, and 6, “simultaneously” encompasses embodiments in which a read operation is initiated during a suspension period and continues into a period in which programming has resumed, such that both operations are occurring concurrently for at least a portion of time.
Regarding claim 7, the combination of Hyun and Shibata teaches the memory device of claim 1, wherein the memory access operation is a read operation ([0051] of Hyun, “…memory control manager 140 may then perform the read operation at the memory elements 126 and retrieve the data stored at the specified address(es)…”, [0038] of Hyun, “…read access request…”).
Regarding claim 8, the combination of Hyun and Shibata teaches the memory device of claim 1, wherein the set of memory cells is a block of the memory array (126 in figure 2 of Hyun, NAND arrays organize in blocks).
Regarding independent claim 9, the combination of Hyun and Shibata teaches a memory device, comprising:
a memory array (126 in figure 2 of Hyun) comprising a plurality of memory cells electrically coupled to a plurality of conductive lines (WL /BL in figure 2 of Hyun); and
a controller (114 in figure 1 of Hyun) coupled to the memory array, the controller to perform operations comprising:
performing a memory programming operation (502 in figure 5 of Hyun) with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a first sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells (figure 3A/3B teaches an ISPP program method, [0054], “…the voltage pulses for a program operation may be performed using an ISPP approach…”);
responsive to receiving a command to perform a memory access operation (504 in figure 5 of Hyun, [0038] of Hyun, “…in response to receiving a read access request…”), suspending the memory programming operation after performing a current programming pulse of the first sequence of programming pulses (yes branch after 506, 508 in figure 5 of Hyun);
automatically resuming the memory programming operation upon initiating the memory access operation and without an externally-initiated resume command (Shibata teaches a NAND memory device in which an ongoing programming operation is interrupted in response to a read-command sequence. As shown in figure 11A and 11B, the externally supplied sequence 00h-Address-30h initiates the read operation. The device therefore performs the following internally controlled sequence: “suspend program and perform read operation” followed by “resume program”. No separate externally supplied resume command is shown or required between the initiation of the read operation and resumption of programming); and
completing the memory access operation (512 in figure 5 of Hyun) by storing one or more data items read from the memory array in a secondary data cache (SDC) associated with the set of memory cells (SDC in [0048]/[0128] of Shibata) associated with the set of memory cells ([0051] of Hyun, “…memory control manager 140 may then perform the read operation at the memory elements 126 and retrieve the data stored at the specified address(es)…”, [0051] of Hyun, “…the data being written to the memory elements 126 stored in the I/O buffer 148 is transferred to a cache buffer 162 for temporary storage while the program operation is suspended…”, [0069] of Hyun, “…a read buffer 402 to store data read from the memory elements 126…”, [0128] of Shibata, “…if the read start command is input, the write (program) operation is suspended and a read operation is performed. The result of the read operation is held in SDC or both SDC and DDC. Then, the last write operation may be resumed during the output of result of the read operation to the external device (program resumption)…”).
Regarding claim 10, the combination of Hyun and Shibata teaches the memory device of claim 9, wherein programming operation data for the programming operation is stored in a page buffer associated with the set of memory cells (400 in figure 4A of Hyun).
Regarding claim 11, the combination of Hyun and Shibata teaches the memory device of claim 9, wherein suspending the memory programming operation further comprises: storing, in a page buffer associated with the set of memory cells, a status of the programming operation ([0036] of Hyun, “…the program suspend module 120 is configured to store information that defines the state or progress of the program operation, including a pulse count at which the current program operation is suspended...”)
Regarding claim 12, the combination of Hyun and Shibata teaches the memory device of claim 9, wherein the memory programming operation further comprises one or more program verify operations to compare threshold voltage levels of the set of memory cells to at least one predefined threshold voltage level ([0030] of Hyun, “…memory elements 126 may be programmed to different states depending on the desired bit configuration for each memory element 126...”, figure 3A/3B teaches an ISPP program method, [0054], “…the voltage pulses for a program operation may be performed using an ISPP approach…”, figure 10 of Shibata teaches program-verify operations using predetermined verify voltages a, b, c to determine whether the threshold voltage of a programed memory cell has reached the applicable verify level, [0128] of Shibata, “…if the read start command is input, the write (program) operation is suspended and a read operation is performed. The result of the read operation is held in SDC or both SDC and DDC. Then, the last write operation may be resumed during the output of result of the read operation to the external device (program resumption)…”).
Regarding claim 13, the combination of Hyun and Shibata teaches the memory device of claim 9, wherein completing the memory access operation is performed simultaneously with performing one or more programming pulses of the resumed memory programming operation ([0133] of Shibata, “…when DDC becomes available or immediately after the input of the read command, the write (program) operation is suspended and a read operation is performed. The read data is subsequently transferred to SDC and then output to the external device. During the output, the last write operation may be resumed...”)
Regarding claim 14, the combination of Hyun and Shibata teaches the memory device of claim 9, wherein the memory access operation is a read operation ([0051] of Hyun, “…memory control manager 140 may then perform the read operation at the memory elements 126 and retrieve the data stored at the specified address(es)…”, [0038], “…read access request…”).
Regarding claim 15, the combination of Hyun and Shibata teaches the memory device of claim 9, wherein the set of memory cells is a block of the memory array (126 in figure 2 of Hyun, NAND arrays organize in blocks).
Regarding independent claim 16, the combination of Hyun and Shibata teaches a memory device, comprising:
a memory array (126 in figure 2 of Hyun) comprising a plurality of memory cells electrically coupled to a plurality of conductive lines (WL /BL in figure 2 of Hyun); and
a controller (114 in figure 1 of Hyun) coupled to the memory array, the controller to perform operations comprising:
performing a memory programming operation (502 in figure 5 of Hyun) with respect to a set of memory cells of the memory array, wherein the memory programming operation (502 in figure 5 of Hyun) comprises a first sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells (figure 3A/3B teaches an ISPP program method, [0054], “…the voltage pulses for a program operation may be performed using an ISPP approach…”);
responsive to receiving a command (504 in figure 5 of Hyun, [0038] of Hyun, “…in response to receiving a read access request…”) to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the first sequence of programming pulses (yes branch after 506, 508 in figure 5 of Hyun), wherein the current programming pulse is performed at a first voltage level;
automatically resuming the memory programming operation upon initiating the memory access operation and without an externally-initiated resume command (Shibata teaches a NAND memory device in which an ongoing programming operation is interrupted in response to a read-command sequence. As shown in figure 11A and 11B, the externally supplied sequence 00h-Address-30h initiates the read operation. The device therefore performs the following internally controlled sequence: “suspend program and perform read operation” followed by “resume program”. No separate externally supplied resume command is shown or required between the initiation of the read operation and resumption of programming);
completing (512 in figure 5 of Hyun), simultaneously with performing one or more programming pulses of the memory programming operation ([0133] of Shibata, “…when DDC becomes available or immediately after the input of the read command, the write (program) operation is suspended and a read operation is performed. The read data is subsequently transferred to SDC and then output to the external device. During the output, the last write operation may be resumed...”), the memory access operation by storing one or more data items read from the memory array in an input/output (I/O) buffer (402 in figure 4A of Hyun, [0069] of Hyun, “…In other embodiments…the memory device 116 includes a program buffer 400 to store data to be written to the memory elements 126 and a read buffer 402 to store data read from the memory elements 126. In such embodiments, the data corresponding to the program operation may be stored in the program buffer 400 and does not need to be transferred to another buffer. The program buffer 400 and the read buffer 402 may be connected to the same sense amplifier 146 or separate sense amplifiers 146 for transferring data between the buffers and the memory elements 126…”) associated with the set of memory cells, wherein the I/O buffer is not utilized by the memory programming operation.
Regarding claim 17, the combination of Hyun and Shibata teaches the memory device of claim 16, wherein programming operation data for the programming operation is stored in a page buffer associated with the set of memory cells (400 in figure 4A of Hyun, [0069] of Hyun, “…In other embodiments…the memory device 116 includes a program buffer 400 to store data to be written to the memory elements 126 and a read buffer 402 to store data read from the memory elements 126. In such embodiments, the data corresponding to the program operation may be stored in the program buffer 400 and does not need to be transferred to another buffer. The program buffer 400 and the read buffer 402 may be connected to the same sense amplifier 146 or separate sense amplifiers 146 for transferring data between the buffers and the memory elements 126…”).
Regarding claim 18, the combination of Hyun and Shibata teaches the memory device of claim 16, wherein the I/O buffer is represented by a secondary data cache (SDC) associated with the set of memory cells (SDC in [0128] of Shibata).
Regarding claim 19, the combination of Hyun and Shibata teaches the memory device of claim 16, wherein suspending the memory programming operation further comprises: storing, in a page buffer associated with the set of memory cells, a status of the programming operation ([0036] of Hyun, “…the program suspend module 120 is configured to store information that defines the state or progress of the program operation, including a pulse count at which the current program operation is suspended...”)
Regarding claim 20, the combination of Hyun and Shibata teaches the memory device of claim 16, wherein the memory programming operation further comprises one or more program verify operations to compare threshold voltage levels of the set of memory cells to at least one predefined threshold voltage level ([0030] of Hyun, “…memory elements 126 may be programmed to different states depending on the desired bit configuration for each memory element 126...”, figure 3A/3B teaches an ISPP program method, [0054], “…the voltage pulses for a program operation may be performed using an ISPP approach…”, figure 10 of Shibata teaches program-verify operations using predetermined verify voltages a, b, c to determine whether the threshold voltage of a programed memory cell has reached the applicable verify level).
Response To Arguments
In regard to amendment of the independent claims 1, 9, and 16, applicant’s arguments have been fully considered and they are persuasive to the extent that Hyun alone does not teach automatic resumption without separately externally initiated resume command. Applicant has amended the independent claims with additional limitation(s): "automatically resuming the memory programming operation upon initiating the memory access operation and without an externally-initiated resume command," The Applicant argues that the prior arts of record do not specifically teach this limitation. However, the independent claim 1 is now rejected as being unpatentable over Hyun in view of Shibata. The Examiner respectfully submits that Hyun teaches all features recited in the independent claim 1, except the newly added limitation. However, Shibata teaches a NAND memory device in which an ongoing programming operation is interrupted in response to a read-command sequence. As shown in figure 11A and 11B, the externally supplied sequence 00h-Address-30h initiates the read operation. The device therefore performs the following internally controlled sequence: “suspend program and perform read operation” followed by “resume program”. No separate externally supplied resume command is shown or required between the initiation of the read operation and resumption of programming. Also, under BRI, “upon initiating the memory access operation” does not require resumption at the identical instant the memory-access operation begins. Applicant’s figure 6 depicts initiating the read operation at step 650, thereafter automatically resuming programming at step 660, and subsequently completing the read operation concurrently with programming at step 670. Accordingly, the phrase encompasses resumption responsive to and as part of the operational sequence triggered by initiation of the memory-access operation. Shibata’s sequence initiated by read-start command 30h, followed suspension, reading, and internally controlled programming resumption, teaches or suggests this limitation. The Examiner respectfully submits that Hyun in view of Shibata teach all limitations recited in claim 1 including the newly added limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Primary Examiner, Art Unit 2824
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