DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/11/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Andy Rudoff, “Persistent memory programming” (hereinafter Rudoff) and further in view of Nemazie et al. (US 2014/0201432 A1).
Claim 1: Rudoff teaches an information handling system (In page 1, col. 2, para. 1-2, Rudoff describes systems with "NVIDIMMs" (Non-Volatile DIMMs) installed, which constitute persistent memory connected to the memory bus alongside traditional DRAM. This is a standard information handling system (e.g., a server or computer)) comprising:
a processor (e.g. a processor is an inherent component of any information handling system capable of utilizing memory DIMMs);
a persistent memory (Rudoff explicitly teaches "persistent memory" and "NVIDIMMs" throughout the article, e.g., "persistent memory installed in the system." See page 2, Col. 1, Para. 2; Fig. 1); and
a basic input/output system communicatively coupled to the processor (Rudoff explicitly teaches the role of the BIOS: "On Intel-based systems, the BIOS creates a table called the NVDIMM Firmware Interface Table (NFIT) that enumerates the NVDIMMs installed." The BIOS is inherently communicatively coupled to the processor to perform this system initialization function. See page 2, Col. 1, Para. 3) and configured to during a first boot of the information handling system write a metadata (see page 2, col. 1, para 1).
While Rudoff teaches the concept of using relative offsets for location independence, Rudoff does not explicitly teach writing such offset values into a persistent metadata region during first boot for use in subsequent boots. However, Nemazie explicitly teaches writing mapping information to a persistent metadata region. For instance, Nemazie teaches "creating and storing a PMM memory address mapping information in a designated, protected persistent memory area" (e.g., claim 4) and "configuring the PMMs to be invisible to the OS during operation mapping the persistent memory modules to an unallocated area of the memory address space; storing the mapping information to a designated protected persistent memory area" (Abstract). Nemazie further teaches that this stored mapping information describes the location of persistent memory within the system address space (e.g., [¶0050]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to apply Rudoff's teaching of using relative offsets for location-independent addressing to Nemazie's system of storing mapping information in persistent metadata. The combination yields: during first boot, writing to a metadata region on persistent memory a floating offset value (as taught by Rudoff) that describes the persistent memory region as a relative location within the system memory map (as taught by Rudoff), with the metadata storage mechanism provided by Nemazie.
Furthermore, Rudoff does not explicitly teach reading previously stored mapping metadata from persistent memory during a later boot. However, Nemazie explicitly teaches reading configuration data stored in persistent memory metadata during system initialization. For instance, Nemazie explicitly teaches that BIOS and drivers detect memory modules and read persistent memory configuration data from module metadata structures such as SPD tables (e.g., [¶0052, ¶0053]) and persistent memory mappings are established using stored configuration data (e.g., [¶0050]). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to combine Rudoff's teaching of using relative offsets for location independence across changing memory maps with Nemazie's teaching of reading persistent metadata during system initialization. The combination yields: during a second boot, reading the floating offset value (as taught by Rudoff) from the metadata region (as taught by Nemazie) to locate the persistent memory region within an updated system memory map.
As per the limitations "wherein the updated system memory map differs from the system memory during the first boot", Rudoff explicitly teaches that memory maps can change between executions: "A security feature known as Address Space Layout Randomization (ASLR) additionally causes operating systems to randomly adjust where libraries and files are mapped" (e.g., p. 5). This directly teaches that the memory map at second boot may differ from the memory map at first boot. And Nemazie teaches that persistent memory modules are dynamically detected and mapped during system initialization by firmware or drivers [¶0050]. Such dynamic configuration inherently allows the memory mapping to change depending on detected modules and system configuration, consistent with Rudoff's explicit teaching.
As per claims 6 and 11, the claimed features are rejected similarly to claim 1 above.
Claim 2: Rudoff teaches the information handling system of Claim 1, but fails to teach that the metadata region is a header of the persistent memory. However, Rudoff teaches that the BIOS writes the NFIT, which is a metadata structure describing the persistent memory. It is a well-known and conventional practice in the art of memory and storage system design to place crucial metadata, such as a root structure or description table, at a fixed, known location—typically at the beginning (a "header") of a memory region or storage device. This allows the OS or other software to easily find it. A POSITA would have been motivated to place the NFIT or a similar BIOS-written metadata structure in a header region of the persistent memory as a matter of standard design practice to facilitate discovery and initialization. This is an obvious implementation choice.
As per claims 7 and 12, the claimed features are rejected similarly to claim 2 above.
Claim 3: Rudoff teaches the information handling system of Claim 1, but fails to teach that the floating memory offset value describes an offset of the memory region of the persistent memory from the top of the system memory map. However, Rudoff teaches that the BIOS defines the system memory map and the placement of the persistent memory within it via the NFIT. Describing a memory region by its offset from the top (a high address) is a standard and common technique in memory management and hardware description. It is functionally equivalent to describing it from the bottom (base address) and simply requires subtracting the offset from the total memory size. A POSITA seeking to implement the "floating memory offset value" taught by Rudoff would consider it an obvious design choice to express this value as an offset from the top of the memory map, as this is a conventional and well-known way to define memory regions, especially for memory-mapped hardware. This is an obvious alternative.
As per claims 8 and 13, the claimed features are rejected similarly to claim 3 above.
Claim 4: Rudoff teaches the information handling system of Claim 1, but fails to teach that the basic input/output system is configured to write entries to a table of the persistent memory wherein such entries refer to offsets within a floating memory offset region defined by the floating memory offset value that identify errors within the persistent memory. However, Rudoff teaches that the BIOS writes the NFIT. The ACPI specification (which defines the NFIT) includes mechanisms for describing platform capabilities and errors. Furthermore, it is a fundamental function of a BIOS and memory controller to track and report memory errors (e.g., via ECC, patrol scrubbing). It would have been obvious to a POSITA to have the BIOS write a table of error information into the persistent memory's metadata region. Using offsets within the defined persistent memory region (the "floating memory offset region") to point to these error entries is the natural and obvious way to maintain position independence, a core principle taught by Rudoff. This is a straightforward combination of memory error management techniques with the position-independent addressing solution taught by Rudoff.
As per claims 9 and 14, the claimed features are rejected similarly to claim 4 above.
Claim 5: Rudoff teaches the information handling system of Claim 4, but fails to teach that the table comprises an address range scrubbing table. However, Rudoff's discussion occurs in the context of NVDIMMs. Address Range Scrubbing (ARS) is a standard and well-known capability of modern memory controllers and BIOSes for actively scanning memory for errors. The ACPI specification includes definitions for ARS. Given that Rudoff teaches the BIOS is responsible for enumerating and describing the persistent memory (a new type of memory hardware), it would have been obvious to a POSITA to extend this function to include managing ARS for that specific memory type. Configuring the BIOS to write an ARS table into the persistent memory's metadata region is a predictable and obvious application of this known error-handling technique to the new persistent memory context disclosed by Rudoff.
As per claims 10 and 15, the claimed features are rejected similarly to claim 4 above.
Conclusion
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 3/17/2026