DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “the second fin-to-fin distance substantially the same as the first fin-to-fin distance” in lines 9 through 10. Claim 6 recites ““the second fin pitch substantially the same as the first fin pitch” in lines 9 through 10. Claim 11 recites ““the second body-to-body distance substantially the same as the first body-to-body distance” in lines 11 through 12.
The TERM, ‘Substantially’
The term "substantially" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Substantially” is defined as "being largely but not wholly that which is specified” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how much the value can deviate from the first fin-to-fin distance, the first fin pitch and the first body-to-body distance. The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target anymore. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target (in this case, the target is the first fin-to-fin distance, the first fin pitch and the first body-to-body distance), and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claims 2-5, 7-10 and 12-16 inherit these deficiencies due to their dependency.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of U.S. Patent No. 12,094,955 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because:
In regards to claim 1, 12,094,955 B2 (claims 1, 7, 13) discloses an integrated circuit structure, comprising: a first pair of semiconductor fins, comprising: a first semiconductor fin; and a second semiconductor fin, the second semiconductor fin spaced apart from the first semiconductor fin by a first fin-to-fin distance; a second pair of semiconductor fins, comprising: a third semiconductor fin; and a fourth semiconductor fin, the fourth semiconductor fin spaced apart from the third semiconductor fin by a second fin-to-fin distance, the second fin-to-fin distance substantially the same as the first fin-to-fin distance; a first epitaxial source or drain region on the first semiconductor fin; a second epitaxial source or drain region on the second semiconductor fin, wherein the second epitaxial source or drain region is not merged nor in contact with the first epitaxial source or drain region; a third epitaxial source or drain region on the third semiconductor fin; and a fourth epitaxial source or drain region on the fourth semiconductor fin, wherein the fourth epitaxial source or drain region is in contact with the third epitaxial source or drain region.
In regards to claim 2, 12,094,955 B2 (claims 3, 9) discloses wherein the first epitaxial source or drain region extends laterally beyond the first semiconductor fin, and wherein the second epitaxial source or drain region extends laterally beyond the second semiconductor fin.
In regards to claim 3, 12,094,955 B2 (claims 4, 10) discloses wherein the first fin-to-fin distance is from a center of a base of the first semiconductor fin to a center of a base of the second semiconductor fin, and wherein the second fin-to-fin distance is from a center of a base of the third semiconductor fin to a center of a base of the fourth semiconductor fin.
In regards to claim 4, 12,094,955 B2 (claims 5, 11) discloses further comprising: a first contact over the first epitaxial source or drain region and the second epitaxial source or drain region; and a second contact over the third epitaxial source or drain region and the fourth epitaxial source or drain region.
In regards to claim 5, 12,094,955 B2 (claims 6, 12) discloses wherein the first contact extends laterally between the first epitaxial source or drain region and the second epitaxial source or drain region.
In regards to claim 6, 12,094,955 B2 (claims 1, 7, 13) discloses an integrated circuit structure, comprising: a first pair of semiconductor fin structures, comprising: a first semiconductor fin structure; and a second semiconductor fin structure, the first and second semiconductor fin structures being spaced at first fin pitch; a second pair of semiconductor fin structures, comprising: a third semiconductor fin structure; and a fourth semiconductor fin structure, the third and fourth semiconductor fin structures being spaced at a second fin pitch, the second fin pitch substantially the same as the first fin pitch; a first source or drain region on the first semiconductor fin structure; a second source or drain region on the second semiconductor fin structure, wherein the second source or drain region is not merged nor in contact with the first source or drain region; a third source or drain region on the third semiconductor fin structure; and a fourth source or drain region on the fourth semiconductor fin structure, wherein the fourth source or drain region is in contact with the third source or drain region.
In regards to claim 7, 12,094,955 B2 (claims 3, 9) discloses wherein the first source or drain region extends laterally beyond the first semiconductor fin structure, and wherein the second source or drain region extends laterally beyond the second semiconductor fin structure.
In regards to claim 8, 12,094,955 B2 (claims 4, 10) discloses wherein the first fin pitch distance is from a center of a base of the first semiconductor fin structure to a center of a base of the second semiconductor fin structure, and wherein the second fin pitch distance is from a center of a base of the third semiconductor fin structure to a center of a base of the fourth semiconductor fin structure.
In regards to claim 9, 12,094,955 B2 (claims 5, 11) discloses further comprising: a first contact over the first source or drain region and the second source or drain region; and a second contact over the third source or drain region and the fourth source or drain region.
In regards to claim 10, 12,094,955 B2 (claims 6, 12) discloses wherein the first contact extends laterally between the first source or drain region and the second source or drain region.
In regards to claim 11, 12,094,955 B2 (claims 1, 7, 13) discloses an integrated circuit structure, comprising: a first pair of three-dimensional semiconductor bodies, comprising: a first three-dimensional semiconductor body having a channel region; and a second three-dimensional semiconductor body having a channel region, the second three-dimensional semiconductor body spaced apart from the first three-dimensional semiconductor body by a first body-to-body distance; a second pair of three-dimensional semiconductor bodies, comprising: a third three-dimensional semiconductor body having a channel region; and a fourth three-dimensional semiconductor body having a channel region, the fourth three-dimensional semiconductor body spaced apart from the third three-dimensional semiconductor body by a second body-to-body distance, the second body-to-body distance substantially the same as the first body-to-body distance; a first epitaxial source or drain region adjacent to a first side of the channel region of the first three-dimensional semiconductor body; a second epitaxial source or drain region adjacent to a first side of the channel region of the second three-dimensional semiconductor body, wherein the second epitaxial source or drain region is not merged nor in contact with the first epitaxial source or drain region; a third epitaxial source or drain region adjacent to a first side of the channel region of the third three-dimensional semiconductor body; and a fourth epitaxial source or drain region adjacent to a first side of the channel region of the fourth three-dimensional semiconductor body, wherein the fourth epitaxial source or drain region is in contact with the third epitaxial source or drain region.
In regards to claim 12, 12,094,955 B2 (claims 2, 8) discloses further comprising: a first gate electrode surrounding at least a top surface and a pair of sidewalls of the channel region of the first three-dimensional semiconductor body and surrounding at least a top surface and a pair of sidewalls of the channel region of the second three-dimensional semiconductor body; and a second gate electrode surrounding at least a top surface and a pair of sidewalls of the channel region of the third three-dimensional semiconductor body and surrounding at least a top surface and a pair of sidewalls of the channel region of the fourth three-dimensional semiconductor body.
In regards to claim 13, 12,094,955 B2 (claims 3, 9) discloses wherein the first epitaxial source or drain region extends laterally beyond the first three-dimensional semiconductor body, and wherein the second epitaxial source or drain region extends laterally beyond the second three-dimensional semiconductor body.
In regards to claim 14, 12,094,955 B2 (claims 4, 10) discloses wherein the first body-to-body distance is from a center of the first three-dimensional semiconductor body to a center of the second three-dimensional semiconductor body, and wherein the second body-to-body distance is from a center the third three-dimensional semiconductor body to a center of the fourth three-dimensional semiconductor body.
In regards to claim 15, 12,094,955 B2 (claims 5, 11) discloses further comprising: a first contact over the first epitaxial source or drain region and the second epitaxial source or drain region; and a second contact over the third epitaxial source or drain region and the fourth epitaxial source or drain region.
In regards to claim 16, 12,094,955 B2 (claims 6, 12) discloses wherein the first contact extends laterally between the first epitaxial source or drain region and the second epitaxial source or drain region.
Claims 1-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11 of U.S. Patent No. 11,640,988 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claims 1, 6 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,127,841 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
EXAMINER’S COMMENTS
Examiner notes that the current application would possibly be in condition for allowance if all 112 issues above are resolved and a properly filed terminal disclaimer was filed by the Applicant and approved.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 October 5, 2026
