DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Objections
The claim(s) is/are objected to because of the following informalities:
Claim 7: it appears that “a physical word line on which a first program operation is performed” in line(s) 4 was meant to be -- the physical word line on which the first program operation is performed --.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 2013/0311711 “Yang”).
Regarding claim 1, Yang discloses a memory device comprising:
a memory block connected to physical word lines (WL1-WLm; fig. 3, further WL1-WL4; fig. 4) each including a plurality of pages (“a memory block comprising NAND strings and pages” para 0067);
a peripheral circuit (controller 1220; fig. 2) configured to perform a program operation of storing data in the plurality of pages (“controller controls the nonvolatile memory to perform a program operation by a unit of plural pages” para 0015); and
control logic configured to control the peripheral circuit,
wherein the program operation (fig. 4, 5) includes a first program operation (LSB program; fig. 5) of programming a threshold voltage (Vth; fig. 5) of memory cells included in the plurality of pages (i.e. of LSB and MSB pages; para 0068-0069) to have a threshold voltage of a state of an erase state (E “1”; fig. 5) or an intermediate state (P0 “0”; fig. 5) and a second program operation (MSB program; fig. 5) of programming the memory cells to have a threshold voltage (Vth; fig. 5) of any one of the erase state (E “1”; fig. 5) and first to n-th program states (P0 “01”, P2 “00”, P3 “10”; fig. 5) (n is a natural number equal to or greater than 2 (i.e. 3 program states; fig. 5)), and
the control logic controls the peripheral circuit to perform a first program operation (LSB program, circle 2; fig. 4) on one of a plurality of pages (i.e. LSB (page 2) of plurality of pages LSB and MSB; fig. 4) included in a selected physical word line (WL2; fig. 4) among the physical word lines (WL1-WL4), and then perform a second program operation (MSB program, circle 3, fig. 4) on one of a plurality of pages (i.e. MSB (page 3) of plurality of pages LSB and MSB; fig. 4) included in a physical word line (WL1; fig. 4) on which a first program operation (LSB program, circle 1; fig. 4) is performed before the selected physical word line (LSB program, circle 1, of physical word line WL1 is performed before the selected physical word line WL2; fig. 4).
Regarding claim 5, Yang discloses the memory device of claim 1, wherein the plurality of pages are commonly connected to any one of the physical word lines (fig. 7, 9).
Regarding claim 6, Yang discloses the memory device of claim 1, wherein each of the physical word lines includes logical word lines respectively connected to the plurality of pages (para 0058+).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 7, 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2013/0311711 “Yang”) in view of Park (US 2018/0090217).
Regarding claim 2, Yang does not expressly disclose the memory device of claim 1, wherein the first program operation includes one program loop, and the second program operation includes a plurality of program loops.
Park discloses the first program operation includes one program loop, and the second program operation includes a plurality of program loops (fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Park for the purpose of reducing stress on the device by selectively performing particular operations and corresponding voltages as required (para 0069 of Park), which is common and well known in the art to prevent memory cell degradation.
Regarding claim 3, Park discloses the memory device of claim 2, wherein the first program operation does not include a verify step of verifying whether the threshold voltage of the memory cells included in the plurality of pages correspond to any one of the erase state or the intermediate state (fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Park for the purpose of reducing stress on the device by selectively performing particular operations and corresponding voltages as required (para 0069 of Park), which is common and well known in the art to prevent memory cell degradation.
Regarding claim 4, Park discloses the memory device of claim 3, wherein each of the plurality of program loops included in the second program operation includes a program voltage apply operation and a verify operation (fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Park for the purpose of reducing stress on the device by selectively performing particular operations and corresponding voltages as required (para 0069 of Park), which is common and well known in the art to prevent memory cell degradation.
Regarding claim 7, Park discloses the memory device of claim 2, wherein the control logic controls the peripheral circuit to apply a program voltage having a level greater by an offset voltage than a program voltage applied to a physical word line on which a first program operation is performed before the selected physical word line in a first program loop among the plurality of program loops, to the selected physical word line during the first program operation (fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Park for the purpose of reducing stress on the device by selectively performing particular operations and corresponding voltages as required (para 0069 of Park), which is common and well known in the art to prevent memory cell degradation.
Regarding claim 9, Park discloses the memory device of claim 1, wherein magnitudes of a pass voltage applied to unselected pages among the plurality of pages during the first program operation and a pass voltage applied to the unselected pages among the plurality of pages during the second program operation have different voltage levels (fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Park for the purpose of reducing stress on the device by selectively performing particular operations and corresponding voltages as required (para 0069 of Park), which is common and well known in the art to prevent memory cell degradation.
Regarding claim 10, Park discloses the memory device of claim 9, wherein the control logic applies pass voltages having different voltage levels to unselected pages adjacent to a selected page corresponding to the physical word line among the unselected pages and remaining unselected pages during the program operation (fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Park for the purpose of reducing stress on the device by selectively performing particular operations and corresponding voltages as required (para 0069 of Park), which is common and well known in the art to prevent memory cell degradation.
Regarding claim 11, Yang discloses the memory device of claim 7, wherein the control logic differently controls a time when a program voltage is applied in the first program operation and a time when the program voltage is applied in the second program operation (fig. 6, 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Park for the purpose of reducing stress on the device by selectively performing particular operations and corresponding voltages as required (para 0069 of Park), which is common and well known in the art to prevent memory cell degradation.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2013/0311711 “Yang”) in view of Park (US 2018/0090217), and further in view of Shim et al. (US 2020/0234782 “Shim”).
Regarding claim 8, Yang, as modified, does not expressly disclose the memory device of claim 7, wherein the offset voltage has different voltage levels according to a position of the physical word line.
Shim discloses wherein the offset voltage has different voltage levels according to a position of the physical word line (para 0107+).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Shim for the purpose of facilitating data accessing schemes by reducing threshold voltage variations (para 0109 of Shim), with is common and well known in the art to improve the integrity of data storage.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hong (US 2019/0189217): teaches a program sequence for storing logical pages of physical word lines.
Kwak (US 2014/0047163): teaches programming method of multi-bit data.
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/UYEN SMET/
[AltContent: connector] Primary Examiner, Art Unit 2824
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