DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lu et al. (Pub. No. US 2025/0224788).
As to claim 1, Lu discloses a power delivery device (fig. 2), comprising:
an inductor 14; and
one or more chips 152a, 152b that are mounted on top of the inductor.
As to claim 2, Lu discloses that the one or more chips are mounted on top of one or more footprints disposed in the inductor (figs. 3, 6).
As to claim 3, Lu discloses that each footprint included in the one or more footprints comprises at least one of an input pin, an output pin, or a ground pin (figs. 6, 7).
As to claim 4, Lu discloses that at least one or more platings or one or more pillars 148a, 148b, 146a, 146b, 154 (fig. 3) that are disposed in one or more sides of the inductor.
As to claim 5, Lu discloses that the at least one or more platings or one or more pillars transmit at least one of power or one or more signals to the one or more chips (¶0057, 0059).
As to claim 6, Lu discloses one or more capacitors C1 that are mounted on one or more sides of the inductor (fig. 3).
As to claim 7, Lu discloses that each chip included in the one or more chips comprises a driver plus metal-oxide-semiconductor field-effect transistor (¶0059).
As to claim 9, Lu discloses that the one or more chips are mounted on top of an interposer 10 that is mounted on top of the inductor.
As to claim 10, Lu discloses that the power delivery device is mounted on a first side of a circuit board 12, and a processor 3 is mounted on a second side of the circuit board (fig. 10).
As to claim 11, Lu discloses a graphics card (fig. 11), comprising:
a circuit board 12;
a graphics processing unit 3 (GPU) (¶0060) mounted on top of a first side of the circuit board; and
one or more power delivery devices mounted on top of a second side of the circuit board, wherein each power delivery device included in the one or more power delivery devices comprises an inductor 14 and one or more chips 152a, 152b disposed on top of the inductor.
As to claim 12, Lu discloses that the one or more chips are mounted on top of the inductor (fig. 11).
As to claim 13, Lu discloses that the one or more chips are mounted on top of one or more footprints disposed in the inductor (figs. 3, 6-7).
As to claim 14, Lu discloses that the one or more chips are mounted on top of an interposer 10, and the interposer is mounted on top of the inductor (figs. 3, 6).
As to claim 15, Lu discloses that the interposer comprises a printed circuit board (PCB) (¶0051).
As to claim 16, Lu discloses that each power delivery device included in the one or more power delivery devices further comprises at least one or more platings or one or more pillars 148a, 146a, 148b, 154 disposed in one or more sides of the inductor included in the power delivery device.
As to claim 17, Lu discloses that wherein the at least one or more platings or one or more pillars are configured to transmit at least one of power or one or more signals to the GPU (¶0057, ¶0059).
As to claim 18, Lu discloses that each power delivery device included in the one or more power delivery devices further comprises one or more capacitors mounted on one or more sides of the inductor included in the power delivery device (fig. 2).
As to claim 19, Lu discloses that each chip included in the one or more chips comprises a driver plus metal-oxide-semiconductor field-effect transistor (¶0059).
As to claim 20, Lu discloses a computer system (fig. 10), comprising:
a processor (¶0060); and
one or more power delivery devices that delivery power to the processor, wherein each power delivery device included in the one or more power delivery devices comprises an inductor 14 on top of which one or more chips are mounted 152a, 152b.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Murase (Pub. No. US 2016/0233017).
As to claim 1, Murase discloses a power delivery device (fig. 19), comprising:
an inductor 10; and
one or more chips 14 that are mounted on top of the inductor.
As to claim 2, Murase discloses that the one or more chips are mounted on top of one or more footprints disposed in the inductor (fig. 19; ¶0102).
As to claim 3, Murase discloses that each footprint included in the one or more footprints comprises at least one of an input pin, an output pin, or a ground pin (fig. 20).
As to claim 4, Murase discloses that at least one or more platings or one or more pillars that are disposed in one or more sides of the inductor (figs. 3A-7B show via conductors on the edges; fig. 8 shows the layers put together forming a conductive pillars).
As to claim 6, Murase discloses one or more capacitors C1 that are mounted on one or more sides of the inductor (fig. 19).
As to claim 8, Murase discloses that at least one or more resistors or one or more capacitors C1 mounted on top of the inductor (fig. 19; ¶0082).
Claim(s) 1, 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (Pub. No. US 2023/0396158).
As to claim 1, Huang discloses a power delivery device (fig. 20), comprising:
an inductor 206; and
one or more chips 203 that are mounted on top of the inductor.
As to claim 7, Huang discloses that each chip included in the one or more chips comprises a driver plus metal-oxide-semiconductor field-effect transistor (¶0055).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMOL H PATEL whose telephone number is (571)270-7833. The examiner can normally be reached 9:30AM-6:00PM.
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/AMOL H PATEL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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