DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant previously filed claims 1-20. No claims have been amended or added. Accordingly, claims 1-20 are pending in the current application.
Response to Arguments
Applicant's arguments filed 04/06/2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “the system transmit blocks to a decoder, not an encoder”; “any specific processor in the parallel multi-processor system is concurrently accessible to different processors”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Firstly, the claim language as filed does not require that blocks are transmitted to an encoder. Secondly, the claim language only requires the concurrent access of a “first hardware computational resource” not specifically a processor or an encoder. Any computational resource which both controllers access concurrently are interpreted to meet this limitation as filed.
Applicant argues that Bruns et al. fails to teach “accessing, by the second controller, a first hardware computational resource to perform a first video encoding function, wherein the first hardware computational resource is concurrently accessible by the first controller and the second controller”. However examiner respectfully disagrees. Bruns et al. in Paragraph 55 teaches “The processor(s) 402 of the encoder/decoder device may be configured to implement part or all of the features described herein, e.g., by executing program instructions stored on a memory medium (e.g., a non-transitory computer-readable memory medium). In some embodiments, the processor(s) 402 may comprise a multiprocessor array of a plurality of parallelized processing elements. For example, the processor(s) 402 may be designed in accordance with the Coherent Logix HyperX™ architecture, or another parallel processor architecture. Alternatively (or in addition), processor(s) 402 may be configured as a programmable hardware element, such as an FPGA (Field Programmable Gate Array), or as an ASIC (Application Specific Integrated Circuit). Alternatively (or in addition) the processor(s) 402 of the encoder/decoder device, in conjunction with one or more of the other components 400, 404, 406, 410, 420, 430, 435, 440, 460 may be configured to implement part or all of the features described herein.” In Paragraph 59 it teaches “FIG. 3 illustrates an example parallel multi-processor system that may be present in an encoder and/or decoder. In this example, the parallel multi-processor system may comprise a plurality of interspersed processors and memories, as shown where the rectangles are processing elements (also called functional units) and the circles are memories, also referred to as data memory routers. For example, one or multiple processing elements may be allocated a subset of columns of a video frame for encoding and/or decoding, as described in greater detail below. In other words, the term “processor” as used in reference to the parallel multi-processor system described herein may refer to either a single processing element or a group of a plurality of processing elements as illustrated in FIG. 3. Advantageously, methods described herein may employ distributed control to parallelize the encoding or decoding process without introducing a master controller to direct the encoding/decoding process.” In Paragraph 94, it further teaches “FIG. 11 is a flowchart diagram illustrating an exemplary method for a parallel multi-processor encoder system to encode and transmit a sequence of video frames, according to some embodiments. The parallel multi-processor encoder system may be comprised within a UE 106, a base station 102, an internet server, or another type of computing device. The parallel multi-processor encoder system may comprise a plurality of parallel processors coupled to respective memory media, and may further comprise a master control processor configured to coordinate activity between the parallel processors. Some of the method elements shown may be performed concurrently, in a different order than shown, or may be omitted. Additional method elements may also be performed as desired. As shown, the method may operate as follows.” In Paragraph 97, it further teaches “At 1104, each subset of blocks may be allocated to a respective processor of the parallel multi-processor system. In some embodiments, the subsets of blocks may be allocated and transmitted to their respective processors. Alternatively, the entire plurality of blocks may be transmitted to each processor and each processor may then divide the plurality of blocks into a respective subset of blocks, and allocate this subset of blocks to itself for encoding.” Thus it is abundantly clear that there may be shared hardware architecture in the parallel processors described, this is interpreted to teach that a first hardware computational resource may be concurrently utilized as claimed.
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
In light of the above remarks, the claims are rejected as before.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, and 9-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bruns et al. (US 20190182495 A1).
Regarding Claim 1, Bruns et al. teaches a computer-implemented method for parallel encoding of multiple block rows in a media frame (Abstract), the method comprising:
encoding, by a first controller, a first plurality of blocks included in a first row of a media frame (Paragraphs 5-11, “Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor”);
encoding, by a second controller in parallel with the first controller encoding the first plurality of blocks, a second plurality of blocks included in a second row of the media frame (Paragraphs 5-11, “Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor”); and
accessing, by the second controller, a first hardware computational resource to perform a first video encoding function, wherein the first hardware computational resource is concurrently accessible by the first controller and the second controller (Paragraphs 5-11; Paragraph 55; Paragraphs 59-60; Paragraphs 94-98).
Regarding Claim 2, Bruns et al. teaches the computer-implemented method of claim 1, wherein the first controller encodes the first plurality of blocks concurrently with the second controller encoding the second plurality of blocks (Paragraphs 5-11).
Regarding Claim 3, Bruns et al. teaches the computer-implemented method of claim 1, wherein the first hardware computational resource comprises a motion estimation unit, and wherein the first video encoding function comprises generating a motion vector for a first block included in the first plurality of blocks, and wherein the motion vector comprises an interframe candidate for the first block (Paragraph 62).
Regarding Claim 4, Bruns et al. teaches the computer-implemented method of claim 3, wherein the first video encoding function further comprises generating motion compensated pixels for the interframe candidate based on the motion vector (Paragraph 62-63).
Regarding Claim 5, Bruns et al. teaches the computer-implemented method of claim 1, wherein the first hardware computational resource comprises an intra search unit, and wherein the first video encoding function comprises selecting an intra prediction mode based on pixel data included in a first block included in the first plurality of blocks and pixel data from neighboring pixels include in a reconstructed media frame of the media frame (Paragraph 61-63; Paragraphs 67-68; Paragraphs 73-80).
Regarding Claim 6, Bruns et al. teaches the computer-implemented method of claim 5, wherein the first video encoding function further comprises generating an intraframe candidate based on the selected intra prediction mode (Paragraph 61-63; Paragraphs 67-68; Paragraphs 73-80).
Regarding Claim 9, Bruns et al. teaches the computer-implemented method of claim 1, wherein the first hardware computational resource comprises a reconstruction unit, and wherein the first video encoding function comprises: generating frequency coefficients by performing an inverse quantization function to reverse a quantization previously performed on a first block included in the first plurality of blocks; and generating reconstructed residue data by performing an inverse transformation function to reverse a transformation previously performed on the first block (Paragraph 61-65; Paragraphs 67-68; Paragraphs 75-76).
Regarding Claim 10, Bruns et al. teaches the computer-implemented method of claim 9, wherein the first video encoding function further comprises: summing the reconstructed residue data with one of an interframe candidate for the first block or an intraframe candidate for the first block to generate a reconstructed block of the first block (Paragraph 61-65; Paragraphs 67-68; Paragraphs 75-76).
Regarding Claim 11, Bruns et al. teaches the computer-implemented method of claim 1, wherein the first hardware computational resource comprises a filter unit, and wherein the first video encoding function comprises filtering a first block included in the first plurality of blocks using at least one of a deblocking filter or a sample adaptive offset filter (Paragraph 61-65; Paragraphs 67-68; Paragraphs 90-92).
Regarding Claim 12, Bruns et al. teaches the computer-implemented method of claim 1, further comprising, subsequent to encoding a first block included in the first plurality of blocks, storing the encoded first block in a shared memory, wherein an entropy encoder generates a bitstream from the encoded first block (Paragraphs 5-11; Paragraphs 35-37; Paragraph 43; Paragraphs 52-53).
Regarding Claim 13, Bruns et al. teaches the computer-implemented method of claim 1, wherein the first plurality of blocks and the second plurality of blocks comprise at least one of macroblocks or coding tree units (CTUs) (Paragraphs 71-72; Paragraphs 82-85).
Regarding Claim 14, Bruns et al. teaches the computer-implemented method of claim 1, wherein the first controller and the second controller are included in a plurality of encoders that are encoding a first group of rows of the media frame, wherein the first group of rows includes the first row and the second row, and further comprising: determining, by the first controller, that encoding of the first plurality of blocks included in the first row of the media frame is complete; and encoding, by the first controller, a third plurality of blocks included in a third row of the media frame, wherein the third row is included in a second group of rows of the media frame (Paragraphs 5-11; Paragraph 55; Paragraphs 59-60; Paragraphs 94-101).
Regarding Claim 15, Bruns et al. teaches the computer-implemented method of claim 14, further comprising: determining, by the second controller, that encoding of the second plurality of blocks included in the second row of the media frame is complete; and encoding, by the second controller, a fourth plurality of blocks included in a fourth row of the media frame, wherein the fourth row is included in the second group of rows of the media frame (Paragraphs 5-11; Paragraph 55; Paragraphs 59-60; Paragraphs 94-101).
Regarding Claim 16, Bruns et al. teaches the computer-implemented method of claim 1, wherein at least one of the first plurality of blocks or the second plurality of blocks is encoded according to any one or more of high efficiency video coding (HEVC) 264 standard (H.264), H.265, H.266, Video comPression format 9 (VP9), or Alliance for Open Media (AOMedia) Video 1 (AV1) (Paragraph 62).
Apparatus Claims 17-19 are drawn to the apparatus corresponding to computer implemented method claims 1, and 3-6 above, and are rejected for the same reasons as used above. Bruns et al. further teaches a computing system (Paragraphs 5-11; Paragraphs 38-42; Paragraph 55; Paragraphs 59-60; Paragraph 119).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, 8 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bruns et al. (US 20190182495 A1) in view of Wang et al. (US 20210409746 A1).
Regarding Claim 7, Bruns et al. teaches the computer-implemented method of claim 1, a first block included in the first plurality of blocks between an interframe candidate for the first block generated by a motion estimation unit and an intraframe candidate for the first block generated by an intra search unit (Paragraph 61-63; Paragraphs 67-68; Paragraphs 73-80).
However, Bruns et al. does not teach wherein the first hardware computational resource comprises a rate-distortion optimization unit, and wherein the first video encoding function comprises selecting a winning candidate.
Wang et al., however, teaches wherein the first hardware computational resource comprises a rate-distortion optimization unit, and wherein the first video encoding function comprises selecting a winning candidate for a first block included in the first plurality of blocks between an interframe candidate for the first block generated by a motion estimation unit and an intraframe candidate for the first block generated by an intra search unit (Paragraphs 32-39; Paragraphs 73-78; Paragraphs 90-94; Paragraphs 96-100; Paragraph 103).
It would have been obvious to a person having ordinary skill in the art at the time of the filing of the invention to have modified the computer implemented method of Bruns et al. to include the rate-distortion based candidates of Wang et al. so video data can be encoded/decoded more efficiently while maintaining the image quality of the decoded video data (See Wang et al. Paragraph 6).
Regarding Claim 8, Bruns et al. and Wang et al. teach the computer-implemented method of claim 7, however, Bruns et al. does not explicitly teach wherein selecting the winning candidate for the first block comprises: determining a rate-distortion cost value based on a sum of square errors (SSE) distortion for the first block; and selecting the winning candidate based at least in part on the rate-distortion cost value.
Wang et al., however, teaches wherein selecting the winning candidate for the first block comprises: determining a rate-distortion cost value based on a sum of square errors (SSE) distortion for the first block; and selecting the winning candidate based at least in part on the rate-distortion cost value (Paragraphs 32-39; Paragraphs 73-78; Paragraphs 90-94; Paragraphs 96-100; Paragraph 103).
It would have been obvious to a person having ordinary skill in the art at the time of the filing of the invention to have modified the computer implemented method of Bruns et al. to include the rate-distortion based candidates of Wang et al. so video data can be encoded/decoded more efficiently while maintaining the image quality of the decoded video data (See Wang et al. Paragraph 6).
Apparatus claim 20 is drawn to the apparatus corresponding to method claims 7-8 rejected above, claim 20 is rejected for the same reasons as used above. Bruns et al. further teaches a computing system (Paragraphs 5-11; Paragraphs 38-42; Paragraph 55; Paragraphs 59-60; Paragraph 119).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARHAN MAHMUD whose telephone number is (571)272-7712. The examiner can normally be reached 10-7.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joseph Ustaris can be reached at 5712727383. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FARHAN MAHMUD/Primary Examiner, Art Unit 2483
Prosecution Insights