DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 08/12/2024. Claims 1-20 are presented for examination and have been considered below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 18/736,147 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because every limitations claimed in the present application is anticipated by the claimed invention of copending Application No. 18/736,147, as follows:
Present application
18/736,147
1. An apparatus, comprising: a hash value calculation circuit; and a plurality of hardware functional units coupled to the hash value calculation circuit via a first bus, wherein the plurality of hardware functional units are individually to autonomously and unilaterally communicate respective sets of data elements to the hash value calculation circuit via the first bus; wherein, responsive at least in part to at least one of the plurality of hardware functional units placing one or more signals representative of at least a first set of data elements on the first bus, the hash value calculation circuit to calculate a first hash value based at least in part on the first set of data elements.
2. The apparatus of claim 1, wherein the hash value calculation circuit is to calculate the first hash value for a current set of instructions of an instruction sequence test operation based at least in part on the first set of data elements and on a previously calculated hash value for a previous set of instructions of the instruction sequence test operation.
3. The apparatus of claim 1, wherein the hash value calculation circuit is further to calculate a plurality of successive hash values for a respective plurality of successive sets of instructions of the instruction sequence test operation based at least in part on one or more additional sets of data elements and further based at least in part on at least one previously calculated hash value from at least one previous set of instructions of the plurality of successive sets of instructions.
4. The apparatus of claim 1, further including a hash value register to store the calculated first hash value.
5. The apparatus of claim 1, further comprising: a control register; and a control signal path to couple the control register to the plurality of hardware functional units; wherein the control register to broadcast one or more configuration bits to the plurality of hardware functional units via the control signal path.
6. The apparatus of claim 5, wherein the plurality of hardware functional units are individually to autonomously and unilaterally determine how to react to the one or more configuration bits.
7. The apparatus of claim 1, further comprising a second control register and a second bus to couple the second control register to the plurality of hardware functional units, wherein the second bus is to communicate one or more enable signals to the at least one of the plurality of hardware functional units based at least in part on one or more second control data elements stored in the second control register.
8. The apparatus of claim 7, wherein the at least one of the plurality of hardware functional units is to place the one or more signals representative of the at least the first set of data elements on the first bus responsive at least in part to the one or more enable signals.
9. The apparatus of claim 7, wherein the hash value calculation circuit is to calculate the first hash value and/or one or more additional hash values responsive at least in part to a hash value calculation enable signal communicated via the second control bus in accordance with a hash value calculation enable bit of the second control register.
10. The apparatus of claim 1, wherein the at least one of the plurality of hardware functional units is to comprise a first buffer to temporarily store the first set of data elements prior to placing the first set of data elements on the first bus.
11. The apparatus of claim 10, further comprising a second buffer to temporarily store at least the first set of data elements placed on the first bus, wherein the second buffer is to provide the at least the first set of data elements to the hash value calculation circuit.
12. The apparatus of claim 1, comprising a processor core comprising a data processing unit and further comprising the plurality of hardware functional units, wherein the data processing unit is to comprise the hash value calculation circuit.
13. The apparatus of claim 1, wherein the respective sets of data elements for the plurality of hardware functional units comprise signals and/or states representative of internal state content for the respective plurality of hardware functional units.
14. The apparatus of claim 1, wherein, to autonomously and unilaterally communicate the respective sets of data elements to the hash value calculation circuit, the plurality of hardware functional units are individually to autonomously and unilaterally: select which content to include in the respective sets of data elements; and/or determine when to place the respective sets of data elements onto the first bus.
15. A method, comprising: autonomously and unilaterally communicating, by individual functional units of a plurality of hardware functional units coupled to a hash value calculation circuit via a first bus, respective sets of data elements to the hash value calculation circuit via the first bus; responsive at least in part to at least one of the plurality of hardware functional units placing one or more signals representative of at least a first set of data elements on the first bus, calculating, by the hash value calculation circuit, a first hash value based at least in part on the first set of data elements; and storing the calculated first hash value in a hash value register.
16. The method of claim 15, further comprising calculating, by the hash value calculation circuit, a plurality of successive hash values for a plurality of successive sets of instructions of an instruction sequence test operation based at least in part on one or more additional sets of data elements and based at least in part on at least one previously calculated hash value.
17. The method of claim 15, further comprising broadcasting one or more configuration bits from a control register to the plurality of hardware functional units via a control bus.
18. The method of claim 17, further comprising autonomously and unilaterally determining, by the individual functional units of the plurality of hardware functional units, how to react to the one or more configuration bits.
19. The method of claim 15, further comprising: communicating one or more enable signals from the control register to the at least one of the plurality of hardware functional units via the control bus based at least in part on one or more control data elements stored in the control register.
20. A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising: a hash value calculation circuit; and a plurality of hardware functional units coupled to the hash value calculation circuit via a first bus, wherein the plurality of hardware functional units are individually to autonomously and unilaterally communicate respective sets of data elements to the hash value calculation circuit via the first bus; wherein, responsive at least in part to at least one of the plurality of hardware functional units placing one or more signals representative of at least a first set of data elements on the first bus, the hash value calculation circuit to calculate a first hash value based at least in part on the first set of data elements.
1. An apparatus, comprising: execution circuitry to execute a current set of instructions of an instruction sequence test operation, wherein the execution circuitry is to store results of the current set of instructions in one or more first data registers; and hash value calculation circuitry to calculate a hash value for the current set of instructions based at least in part on one or more data elements obtained from one or more specified data registers, including at least the one or more first data registers, and further based at least in part on a previously-calculated hash value for a previous set of instructions of the instruction sequence test operation.
2. The apparatus of claim 1, wherein the current set of instructions comprises one or more instructions and wherein the previous set of instructions comprises one or more instructions to immediately precede the current set of instructions.
3. The apparatus of claim 1, wherein the current set of instructions comprises a single instruction and wherein the previous set of instructions comprises a single instruction to immediately precede the current set of instructions.
4. The apparatus of claim 1, further including a hash value register to store the calculated hash value for the current set of instructions.
5. The apparatus of claim 1, wherein the hash value for the current set of instructions comprises a cyclic redundancy check value for the current set of instructions, and wherein the hash value for the previous set of instructions comprises a cyclic redundancy check value for the previous set of instructions.
6. The apparatus of claim 5, wherein the hash value calculation circuitry comprises circuitry to calculate the cyclic redundancy check value for the current set of instructions based at least in part on the one or more data elements obtained from the one or more specified data registers, including at least the one or more first data registers, and further based at least in part on the cyclic redundancy check value for the previous set of instructions.
7. The apparatus of claim 1, further comprising selection circuitry to indicate to the hash value calculation circuitry the one or more specified data registers.
8. The apparatus of claim 7, wherein the selection circuitry comprises a selection register to store one or more data elements indicative of the one or more specified data registers.
9. The apparatus of claim 1, further comprising a control circuit to enable, halt, and/or pause calculation of hash values by the hash value calculation circuitry responsive at least in part to a first specified value written to a control register.
10. The apparatus of claim 9, wherein the control circuit is to reset the hash value register responsive at least in part to a second specified value written to the control register.
11. The apparatus of claim 1, further comprising: a selection register to store one or more data elements indicative of the one or more specified data registers; a control register to store one or more data elements to indicate to a control circuit to enable, halt, reset, and/or pause calculation of hash values; and a hash value register to store the calculated hash value for the current set of instructions; wherein the selection register, the control register, and/or the hash value register are accessible via execution of one or more instructions.
12. The apparatus of claim 1, wherein the execution circuitry and the hash value calculation circuitry are located in a first processor core.
13. The apparatus of claim 1, wherein the one or more data elements obtained from the one or more specified data registers comprise the previously-calculated hash value.
14. The apparatus of claim 1, further comprising circuitry to, responsive to a calculation of the hash value for the current set of instructions, write the hash value for the current set of instructions from the hash value register to at least one of the one or more specified data registers for use in a subsequent set of instructions to be executed by the execution circuitry as part of the instruction sequence test operation.
15. The apparatus of claim 1, further comprising circuitry to, responsive to a calculation of the hash value for the current set of instructions wherein execution of the current set of instructions is to have cleared at least one of the one or more specified data registers, write the hash value for the current set of instructions from the hash value register to the at least one of the one or more specified data registers.
16. A method, comprising: executing, by execution circuitry of a first processor core, a current set of instructions of an instruction sequence test operation, including storing results of the current set of instructions in one or more first data registers; calculating, via hash value calculation circuitry of the first processor core, a hash value for the current set of instructions based, at least in part, on one or more data elements obtained from one or more specified data registers, including at least the one or more first data registers, and further based at least in part on a previously-calculated hash value for a previous set of instructions of the instruction sequence test operation; and storing the calculated hash value for the current iteration in a hash value register.
17. The method of claim 16, further comprising: writing one or more data elements indicative of the one or more specified data registers in a selection register; writing one or more data elements to a control register to indicate to a control circuit to enable, halt, reset, and/or pause calculation of hash values; and writing the hash value for the current set of instructions to a memory in accordance with one or more additional instructions decoded by an instruction decode unit; wherein the selection register, the control register, and/or the hash value register are accessible via execution of one or more instructions.
18. The method of claim 16, further comprising, responsive to the calculation of the hash value for the current set of instructions, writing the calculated hash value for the current set of instructions from the hash value register to at least one of the one or more specified data registers for use in a subsequent set of instructions to be executed by the execution circuitry as part of the instruction sequence test operation.
19. The method of claim 16, further comprising writing the hash value for the current set of instructions from the hash value register to at least one of the one or more specified data registers responsive to the calculating the hash value for the current set of instructions wherein executing the current set of instructions results in clearing the at least one of the one or more specified data registers.
20. A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising: execution circuitry to execute a current set of instructions of an instruction sequence test operation, wherein the execution circuitry is to store results of the current set of instructions in one or more first data registers; and hash value calculation circuitry to calculate a hash value for the current set of instructions based at least in part on one or more data elements obtained from one or more specified data registers, including at least the one or more first data registers, and further based at least in part on a previously-calculated hash value for a previous set of instructions of the instruction sequence test operation.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over SPRACR3A – Texas Instruments, “CRC Engines in C2000™ Devices (hereinafter SPRACR3A) and further in view of WCAS – Dawood Alnajjar and Mauricio Suguiy, “A Comprehensive Guide for CRC Hardware Implementation (hereinafter WCAS).
Claim 1: SPRACR3A teaches an apparatus, comprising:
a hash value calculation circuit (e.g., BGCRC, VCU CRC – page 2, section 2 and page 4, section 4);
and a plurality of hardware functional units (e.g. CPU, CLA, and DMA) coupled to the hash value calculation circuit via a first bus, (e.g. SPRACR3A teaches that multiple masters such as CPU, CLA, and DMA can access memory or CRC units via shared buses. For instance, BGCRC works during idle time when other masters (CPU, CLA, DMA) are not accessing memory (page 2, lines 15–20).This implies a shared memory bus architecture where multiple functional units (CPU, CLA, DMA) are connected to memory and CRC units via a bus);
wherein, responsive at least in part to at least one of the plurality of hardware functional units placing one or more signals representative of at least a first set of data elements on the first bus, the hash value calculation circuit to calculate a first hash value based at least in part on the first set of data elements (e.g. In BGCRC, CRC computation is triggered when data is read from memory during idle cycles (page 2, lines 15–20) and in GCRC, CPU/DMA writes data to a specific register in the GCRC module to trigger CRC calculation (page 3, lines 5–8).This teaches that placing data on a bus (or writing to a register) triggers CRC calculation).Not explicitly taught by SPRACR3A is that the plurality of hardware functional units are individually to autonomously and unilaterally communicate respective sets of data elements to the hash value calculation circuit via the first bus. However, WCAS discusses parallel CRC implementations where data is fed into the CRC unit via a datapath/bus (page 2, Figure 2, “CRC32 parallel implementation with variable width processing”). Also, WCAS also implies standard bus-based data transfer for CRC calculation in high-speed communication interfaces (e.g., PCIe, Ethernet), where multiple sources (functional units) send data to a CRC unit over a shared data path. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the system of SPRACR3A by adopting the shared bus architecture taught in WCAS, because WCAS teaches that CRC units in communication systems are often connected via shared datapaths/buses to allow efficient data transfer from multiple sources. And it is a common design practice in multi-master digital systems to allow masters to unilaterally initiate transactions on a shared bus (standard bus arbitration). Thus, combining SPRACR3A’s dedicated CRC hardware with WCAS’s bus-based data delivery scheme yields the claimed apparatus without inventive step.
As per claim 20, the claimed features are rejected similarly to claim 1 above.
Claim 2: SPRACR3A and WCAS teach the apparatus of claim 1, but fail to teach that the hash value calculation circuit is to calculate the first hash value for a current set of instructions of an instruction sequence test operation based at least in part on the first set of data elements and on a previously calculated hash value for a previous set of instructions of the instruction sequence test operation. However, SPRACR3A teaches incremental CRC calculation for program integrity checking. ERAD CRC monitors CPU buses during self-test code execution and computes CRC iteratively (page 5, section 6.1). This implies using previous CRC values (hash) for successive instructions. And WCAS discusses incremental CRC implementations where current CRC depends on previous CRC (page 2, property 2(b))). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to apply incremental calculation to instruction-sequence testing for continuous integrity monitoring.
Claim 3: SPRACR3A and WCAS teach the apparatus of claim 1, wherein the hash value calculation circuit is further to calculate a plurality of successive hash values for a respective plurality of successive sets of instructions of the instruction sequence test operation based at least in part on one or more additional sets of data elements and further based at least in part on at least one previously calculated hash value from at least one previous set of instructions of the plurality of successive sets of instructions (for instance, SPRACR3A’s ERAD CRC and CLA-PSA compute successive signatures for program sequences – page 5, section 6.1).
Claim 4: SPRACR3A and WCAS teach the apparatus of claim 1, further including a hash value register to store the calculated first hash value (for instance, SPRACR3A teaches CRC result registers (e.g., CRC result register in GCRC, BGCRC). And WCAS shows CRC registers in Figures 1–2).
Claim 5: SPRACR3A and WCAS teach the apparatus of claim 1, but fail to teach a control register; and a control signal path to couple the control register to the plurality of hardware functional units; wherein the control register to broadcast one or more configuration bits to the plurality of hardware functional units via the control signal path. However, SPRACR3A teaches configuration registers for CRC modules (e.g., BGCRC configuration, MPSACTL for CLA-PSA) and WCAS discusses control signals for CRC enable/disable (page 2). Using a control bus to broadcast configuration bits to multiple functional units is a standard design practice in multi-master systems (e.g., AHB/APB buses). Therefore, before the effective filing date of the claimed invention, it would have been would obvious to a POSITA to employ such a control bus to coordinate CRC operations among masters.
Claim 6: SPRACR3A and WCAS teach the apparatus of claim 5, wherein the plurality of hardware functional units are individually to autonomously and unilaterally determine how to react to the one or more configuration bits (for instance, SPRACR3A’s masters (CPU, CLA, DMA) already operate independently based on their programmed tasks. WCAS implies that units react to control signals based on their local logic).
Claim 7: SPRACR3A and WCAS teach the apparatus of claim 1, but fail to teach a second control register and a second bus to couple the second control register to the plurality of hardware functional units, wherein the second bus is to communicate one or more enable signals to the at least one of the plurality of hardware functional units based at least in part on one or more second control data elements stored in the second control register. However, SPRACR3A teaches separate control registers for enabling CRC operations (e.g., MPSACTL controls PSA enable) and WCAS shows enable/disable control for CRC circuits. Therefore, adding a second control register and bus for enable signals would have been an obvious duplication of control paths for finer-grained management, a common technique in hardware design to a POSITA, before the effective filing date of the claimed invention.
Claim 8: SPRACR3A and WCAS teach the apparatus of claim 7, but fail to teach that the at least one of the plurality of hardware functional units is to place the one or more signals representative of the at least the first set of data elements on the first bus responsive at least in part to the one or more enable signals. However, SPRACR3A’s BGCRC operates when enabled and during idle cycles and WCAS discusses triggering CRC calculation via control signals. Therefore, a POSITA, before the effective filing date of the claimed invention, would have routinely designed functional units to place data on the bus only when enabled.
Claim 9: SPRACR3A and WCAS teach the apparatus of claim 7, wherein the hash value calculation circuit is to calculate the first hash value and/or one or more additional hash values responsive at least in part to a hash value calculation enable signal communicated via the second control bus in accordance with a hash value calculation enable bit of the second control register (Same as claim 8. SPRACR3A’s CRC modules are enabled via control bits).
Claim 10: SPRACR3A and WCAS teach the apparatus of claim 1, but fail to teach that the at least one of the plurality of hardware functional units is to comprise a first buffer to temporarily store the first set of data elements prior to placing the first set of data elements on the first bus. However, SPRACR3A implies buffering in DMA/CPU transfers, and WCAS shows buffers in CRC datapaths (Figure 2). Therefore, a POSITA, because the effective filing date of the claimed invention, would have routinely included buffers in a multi-master bus system because buffering data before placing it on a bus is a well-known technique to manage data flow and avoid bus contention.
Claim 11: SPRACR3A and WCAS teach the apparatus of claim 10, further comprising a second buffer to temporarily store at least the first set of data elements placed on the first bus, wherein the second buffer is to provide the at least the first set of data elements to the hash value calculation circuit (Same as claim 10. Double buffering is common in bus-based systems).
Claim 12: SPRACR3A and WCAS teach the apparatus of claim 1, comprising a processor core comprising a data processing unit and further comprising the plurality of hardware functional units, wherein the data processing unit is to comprise the hash value calculation circuit (for instance, SPRACR3A’s CRC engines are integrated into processor cores (C28x, CLA, CM). WCAS describes CRC units as part of processor datapaths).
Claim 13: SPRACR3A and WCAS teach the apparatus of claim 1, but fail to teach that the respective sets of data elements for the plurality of hardware functional units comprise signals and/or states representative of internal state content for the respective plurality of hardware functional units. However, SPRACR3A’s ERAD CRC monitors CPU bus signals and internal states for integrity checking (page 5) and WCAS processes internal state data for CRC. Therefore, using signals representative of internal state content for hash calculation would have been an obvious application of CRC for diagnostic and testing purposes to a POSITA before the effective filing date of the claimed invention.
Claim 14: SPRACR3A and WCAS teach the apparatus of claim 1, but fail to teach to autonomously and unilaterally communicate the respective sets of data elements to the hash value calculation circuit, the plurality of hardware functional units are individually to autonomously and unilaterally: select which content to include in the respective sets of data elements; and/or determine when to place the respective sets of data elements onto the first bus. However, SPRACR3A’s masters independently decide when to access memory and WCAS implies arbitration and selection in bus-based designs. Therefore, allowing each functional unit to select what content to send and when to send it is inherent in any autonomous multi-master bus system and would have been a routine design consideration to a POSITA before the effective filing date of the claimed invention.
Claim 15: This method claim corresponds directly to apparatus claim 1, with the added step of storing the hash value in a register. SPRACR3A discloses the method of CRC calculation via bus access, and WCAS discloses the method of CRC calculation in hardware. Storing the result in a register is inherent (see claim 4).
Claim 16: Method of calculating successive hash values for instruction sequence test (Same as claim 3. SPRACR3A’s ERAD CRC/CLA-PSA perform successive signature calculations for instruction sequences).Claim 17: Method of broadcasting configuration bits via control bus (Same as claim 5. SPRACR3A discloses configuring CRC modules via control registers).
Claim 18: Method of units autonomously determining how to react to configuration bits (Same as claim 6).
Claim 19: Method of communicating enable signals via control bus (Same as claim 7–9).
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/GUERRIER MERANT/
Primary Examiner,
Art Unit 2111
1/8/2026