DETAILED ACTION
This application is responsive to the following: the application and information disclosure statement filed on August 13, 2024.
Claims 1-20 are pending. Claims 1, 15, and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 13, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-11, 15, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii et al (US 20180122458 A1) in view of Chandwani et al (US 20140185366 A1).
Regarding Independent Claim 1, Ishii teaches a memory device (Fig. 1: 20), comprising:
a first memory array (Fig. 1: 12), comprising a plurality of first memory cells (Fig. 1: MC), arranged in a two-dimensional array having a plurality of first word lines (Fig. 1: WL0-WLi) and a plurality of first bit lines (Fig. 1: BL0-BLm); and
a memory control circuit (Fig. 1: 10, 11, 13), configured to control the first memory array (Fig. 1: 12) and receive a first memory access command (Fig. 1: WE) and a second memory access command (Fig. 1: SE);
wherein the memory control circuit (Fig. 1: 10, 11, 13) is configured to perform a first memory access operation (para 38 “The memory unit 20 functions as a pseudo two-port memory by performing both read and write operations in one cycle of the clock signal CLK input from the clock pulse generator circuit.”) associated with the first memory access command (Fig. 1: WE) in response to a first clock pulse (Fig. 5: TDEC, T2) of a control internal clock signal (Fig. 4: TDEC) generated from a first internal clock signal (Fig. 4: CLKP) and a second internal clock signal (Fig. 4: CLKP2),
wherein the memory control circuit (Fig. 1: 10, 11, 13) is configured to generate a first reset signal (Fig. 4: BACK) and generate a second reset signal (Fig. 4: BACKDLY) using the first reset signal (Fig. 4: BACK),
wherein the memory control circuit (Fig. 1: 10, 11, 13) is configured to generate a second clock pulse (Fig. 5: TDEC, T7) of the control internal clock signal (Fig. 5: TDEC) in response to the second reset signal (Fig. 5: BACKDLY, T5), and perform a second memory access operation (para 38 “The memory unit 20 functions as a pseudo two-port memory by performing both read and write operations in one cycle of the clock signal CLK input from the clock pulse generator circuit.”) associated with the second memory access command (Fig. 1: SE) within the second clock pulse (Fig. 5: TDEC, T7).
Ishii fails to teach a first precharge signal and a second bit-line precharge signal obtained from the first bit-line precharge signal.
Chandwani teaches a first precharge signal (Fig. 1: GRDL_PRCH) and a second bit-line precharge signal (Fig. 1 : TRACK_GRDL_ PRCH) obtained from the first bit-line precharge signal (Fig. 1: GRDL_PRCH).
Chandwani teaches that a pre-charge tracking solves the issue of “High speed static random access memory (SRAM) architectures typically use a sense amplifier and two global read lines to load data into an output latch in a global input output (GIO) Block. This requires two operations finished before the sense amplifier starts discharging one of the global read lines. The first operation is a precharging of the global read lines should get completed before a sense amplifier enable signal arrives. The second operation is the global read lines precharging operation should is finished to avoid contention on the global read lines before the sense amplifier starts discharging one of the global read lines. Across various pressure, voltage and temperatures (PVTs) and instance sizes, it is difficult to meet the above two margin conditions and failure to meet these margins results in functional failure of the SRAMs and huge dynamic power consumption.” (para 1) Thus it would be useful to incorporate bit line precharge tracking into the time of operations of SRAM memories in order to conserve power consumption and margin.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Chandwani to the teachings of Ishii to teach an internal clock generating circuit that resets in response to the bit line precharge signal in addition to the a first reset signal generated by the internal clocks.
Regarding Claim 2, Ishii and Chandwani teach the limitations of Claim 1. Ishii further teaches wherein the memory control circuit (Fig. 1: 10, 11, 13) is configured to receive an input clock signal (Fig. 4: CLK) and generate the first internal clock signal (Fig. 4: CLKP) using the input clock signal.
Regarding Claim 3, Ishii and Chandwani teach the limitations of Claim 2. Ishii further teaches wherein the memory control circuit (Fig. 1: 10, 11, 13) is configured to generate the second internal clock signal (Fig. 4: CLKP2) and a switch control signal using the second reset signal (Fig. 4: BACKDLY).
Regarding Claim 4, Ishii and Chandwani teach the limitations of Claim 3. Ishii further teaches wherein the memory control circuit (Fig. 1: 10, 11, 13) uses a first address signal (Fig. 1: Y0-Yj) and a first write enable signal (Fig. 1: WE) indicated by the first memory access command to perform the first memory access operation (para 38 “The memory unit 20 functions as a pseudo two-port memory by performing both read and write operations in one cycle of the clock signal CLK input from the clock pulse generator circuit.”) in response to the switch control signal being in a first logic state (Fig. 5: BURST, T2-T7).
Regarding Claim 8, Ishii and Chandwani teach the limitations of Claim 4. Chandwani further teaches wherein a routing path of a conductive wire of the first bit-line precharge signal (Fig. 1: GDL_PRCH) extends from the memory control circuit (Fig. 1: 116, 118, 120, 122) to a middle portion of a data input/output circuit, and returns from the middle portion (Fig. 1: Return from the half way to the right) to the memory control circuit to generate the second bit-line precharge signal (Fig. 1: TRACK_GRDL_PRCH).
Regarding Claim 9, Ishii and Chandwani teach the limitations of Claim 8. Chandwani further teaches wherein the routing path is through a buffer (Fig. 1: 112) disposed at the middle portion (Fig. 1: Return from the half way to the right).
Regarding Claim 10, Ishii and Chandwani teach the limitations of Claim 4. Ishii further teaches wherein the memory control circuit switches the switch control signal (Fig 5: BURST T7) to a second logic state different from the first logic state in response to detecting a falling edge of the second reset signal (Fig. 5: BACKDLY, T5).
Regarding Claim 11, Ishii and Chandwani teach the limitations of Claim 10. Ishii further teaches wherein the memory control circuit (Fig. 1: 10, 11, 13) uses a second address signal (Fig. 8: YS) and a second write enable signal (Fig. 8: WES) indicated by the second memory access command (Fig. 8: CES) to perform the second memory access operation in response to the switch control signal being in the second logic state (Fig. 9: BURST, T37).
Regarding Independent Claim 15, Ishii teaches a memory device (Fig. 1: 20), comprising:
a memory array (Fig. 1: 12), comprising a plurality of memory cells (Fig. 1: MC), arranged in a two-dimensional array having a plurality of word lines (Fig. 1: WL0-WLi) and a plurality of bit lines (Fig. 1: BL0-BLm); and
a memory control circuit (Fig. 1: 10, 11, 13), configured to control the memory array (Fig. 1: 12) and receive a first memory access command (Fig. 1: WE) and a second memory access command (Fig. 1: SE);
wherein the memory control circuit (Fig. 1: 10, 11, 13) is configured to perform a first memory access operation (para 38 “The memory unit 20 functions as a pseudo two-port memory by performing both read and write operations in one cycle of the clock signal CLK input from the clock pulse generator circuit.”) associated with the first memory access command (Fig. 1: WE) in response to a first clock pulse (Fig. 5: TDEC, T2) of a control internal clock signal (Fig. 5: TDEC) generated from a first internal clock signal (Fig. 4: CLKP) and a second internal clock signal (Fig. 4: CLKP2),
wherein the memory control circuit (Fig. 1: 10, 11, 13) is configured to generate a first reset signal (Fig. 4: BACK) and generate a second reset signal (Fig. 4: BACKDLY) using the first reset signal (Fig. 4: BACK),
wherein the memory control circuit (Fig. 1: 10, 11, 13) is configured to generate a second clock pulse (Fig. 5: TDEC, T7) of the control internal clock signal (Fig. 5: TDEC) in response to the second reset signal (Fig. 5: BACKDLY, T5), and perform a second memory access operation (para 38 “The memory unit 20 functions as a pseudo two-port memory by performing both read and write operations in one cycle of the clock signal CLK input from the clock pulse generator circuit.”) associated with the second memory access command (Fig. 1: SE) within the second clock pulse (Fig. 5: TDEC, T7).
Ishii fails to teach a first precharge signal and a second bit-line precharge signal obtained from the first bit-line precharge signal.
Chandwani teaches a first precharge signal (Fig. 1: GRDL_PRCH) and a second bit-line precharge signal (Fig. 1 : TRACK_GRDL_ PRCH) obtained from the first bit-line precharge signal (Fig. 1: GRDL_PRCH).
Chandwani teaches that a pre-charge tracking solves the issue of “High speed static random access memory (SRAM) architectures typically use a sense amplifier and two global read lines to load data into an output latch in a global input output (GIO) Block. This requires two operations finished before the sense amplifier starts discharging one of the global read lines. The first operation is a precharging of the global read lines should get completed before a sense amplifier enable signal arrives. The second operation is the global read lines precharging operation should is finished to avoid contention on the global read lines before the sense amplifier starts discharging one of the global read lines. Across various pressure, voltage and temperatures (PVTs) and instance sizes, it is difficult to meet the above two margin conditions and failure to meet these margins results in functional failure of the SRAMs and huge dynamic power consumption.” (para 1) Thus it would be useful to incorporate bit line precharge tracking into the time of operations of SRAM memories in order to conserve power consumption and margin.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Chandwani to the teachings of Ishii to teach an internal clock generating circuit that resets in response to the bit line precharge signal in addition to the a first reset signal generated by the internal clocks.
Regarding Independent Claim 18, Ishii teaches a method for maintaining a time margin between consecutive memory access operations, for use in a memory device (Fig. 1: 20), wherein the memory device (Fig. 1: 20) comprises a memory array (Fig. 1: 12) and a memory control circuit (Fig. 1: 10, 11, 13), the method comprising:
utilizing the memory control circuit (Fig. 1: 10, 11, 13) to receive a first memory access command (Fig. 1: WE) and a second memory access command (Fig. 1: SE);
utilizing the memory control circuit (Fig. 1: 10, 11, 13) to perform a first memory access operation (para 38 “The memory unit 20 functions as a pseudo two-port memory by performing both read and write operations in one cycle of the clock signal CLK input from the clock pulse generator circuit.”) associated with the first memory access command (Fig. 1: WE);
utilizing the memory control circuit (Fig. 1: 10, 11, 13) to generate a first reset signal (Fig. 4: BACK) in response to completion of the first memory access command;
utilizing the memory control circuit (Fig. 1: 10, 11, 13) to generate a second reset signal (Fig. 4: BACKDLY) using the first reset signal (Fig. 4: BACK); and
utilizing the memory control circuit (Fig. 1: 10, 11, 13) to generate a second clock pulse (Fig. 5: TDEC, T7) of the control internal clock (Fig. 5: TDEC) using the second reset signal (Fig. 5: BACKDLY, T5) and to perform a second memory access operation (para 38 “The memory unit 20 functions as a pseudo two-port memory by performing both read and write operations in one cycle of the clock signal CLK input from the clock pulse generator circuit.”) associated with the second memory access command (Fig. 1: SE).
Ishii fails to teach utilizing the memory control circuit to assert a first bit-line precharge signal in response to detecting a falling edge of a first clock pulse of a control internal clock and a second bit-line precharge signal obtained through a routing path of a conductive wire of the first bit-line precharge signal;
Chandwani teaches utilizing the memory control circuit (Fig. 1: 116, 118, 120, 122) to assert a first bit-line precharge signal (Fig. 1: GRDL_PRCH) in response to detecting a falling edge of a first clock pulse (Fig. 4: 404, 406) of a control internal clock (Fig. 4: GRDL_PRCH) and a second bit-line precharge (Fig. 1: TRACK_GRDL_PRCH) signal obtained through a routing path of a conductive wire of the first bit-line precharge signal (Fig. 1: Return from the half way to the right).
Chandwani teaches that a pre-charge tracking solves the issue of “High speed static random access memory (SRAM) architectures typically use a sense amplifier and two global read lines to load data into an output latch in a global input output (GIO) Block. This requires two operations finished before the sense amplifier starts discharging one of the global read lines. The first operation is a precharging of the global read lines should get completed before a sense amplifier enable signal arrives. The second operation is the global read lines precharging operation should is finished to avoid contention on the global read lines before the sense amplifier starts discharging one of the global read lines. Across various pressure, voltage and temperatures (PVTs) and instance sizes, it is difficult to meet the above two margin conditions and failure to meet these margins results in functional failure of the SRAMs and huge dynamic power consumption.” (para 1) Thus it would be useful to incorporate bit line precharge tracking into the time of operations of SRAM memories in order to conserve power consumption and margin.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Chandwani to the teachings of Ishii to teach a method of generating an internal clock signal that resets in response to the bit line precharge signal in addition to the a first reset signal generated by the internal clocks.
Regarding Claim 20, Ishii and Chandwani teach the limitations of Claim 18. Ishii teaches utilizing the memory control circuit (Fig. 1: 10, 11, 13) to alternate a logic state of a switch control signal (Fig. 8: BURST) using the second reset signal (Fig. 8: BACKDLY) to switch from the first memory access operation to the second memory access operation.
Allowable Subject Matter
Claims 5-7, 12-14, 16-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 5, and 19 require the limitation of routing signals to the edge of the array in order to produce a delayed signal for timing purposes within the control circuit. Chandwani teaches routing signals from parts of the center of the array to produce a delayed signal for timing purposes in the control circuit but fails to teach routing to an edge portion of the array. Therefore, these claims would be allowable if written in independent form.
Claims 6 and 7 would be allowable for being dependent on claim 5.
Claim 12 requires the limitation of a second memory array on opposite sides of the word line driving circuit with a second separate set of word lines and bit lines and separate address space. Neither Ishii nor Chandwani teach a second memory array. Therefore, this claim would be allowable if written in independent form.
Claim 13 would be allowable for being dependent on Claim 12.
Claims 14 and 16 teaches the limitation that the internal control clock and the trigger signal are combined in an OR operation to produce the first reset signal. Ishii and Chandwani teach reset signals but fail to teach that they are generated by performing an OR operation on signals that are analogous to these. Therefore, this claim would be allowable if written in independent form.
Claim 17 would be allowable for being dependent on Claim 16.
Conclusion
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825