DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong(USPGPUB DOCUMENT: 2017/0062387, hereinafter Hong) in view of Chung (USPGPUB DOCUMENT: 2022/0216190, hereinafter Chung).
Re claim 1 Hong discloses a semiconductor package comprising: a lower redistribution structure(upper130/lower130); a lower semiconductor chip(IC1/IC2) on the lower redistribution structure(upper130/lower130); and an upper redistribution structure(upper130/lower130) on the lower semiconductor chip(IC1/IC2) and comprising a signal pad(upper110/lower110), and an upper insulation layer(ILD1/ILD2/ILD4), wherein the signal pad(upper110/lower110), and wherein the vertical direction is perpendicular to an upper surface of the lower redistribution structure(upper130/lower130).
Hong does not disclose an upper redistribution structure(upper130/lower130) on the lower semiconductor chip(IC1/IC2) and comprising a signal pad(upper110/lower110), a power pad, a grounding plane, and an upper insulation layer(ILD1/ILD2/ILD4), wherein the signal pad(upper110/lower110), the power pad, and the grounding plane are in the upper insulation layer(ILD1/ILD2/ILD4), wherein a distance between the signal pad(upper110/lower110) and the lower redistribution structure(upper130/lower130) in a vertical direction is less than a distance between the power pad and the lower redistribution structure(upper130/lower130) in the vertical direction,
Chung disclose a semiconductor chip comprising a signal pad(IO of Chung), a power pad(VP1/VP2 of Chung), a grounding plane(since the ground is straight to or aligned with ground this may be interpreted as a plane)[0020 of Chung], and an upper insulation layer(ILD1/ILD2/ILD4)(241/242/250 of Chung), wherein the signal pad(upper110/lower110), the power pad, and the grounding plane are in the upper insulation layer(ILD1/ILD2/ILD4),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chung to the teachings of Hong in order to improve reliability and durability of semiconductor packages [0003, Chung]. In doing so, an upper redistribution structure(upper130/lower130) on the lower semiconductor chip(IC1/IC2) and comprising a signal pad(upper110/lower110), a power pad(VP1/VP2 of Chung), a grounding plane(since the ground is straight to or aligned with ground this may be interpreted as a plane)[0020 of Chung], and an upper insulation layer(ILD1/ILD2/ILD4)(241/242/250 of Chung), wherein the signal pad(upper110/lower110), the power pad, and the grounding plane are in the upper insulation layer(ILD1/ILD2/ILD4),
Although the combination of Hong and Chung do not disclose wherein a distance between the signal pad(upper110/lower110) and the lower redistribution structure(upper130/lower130) in a vertical direction is less than a distance between the power pad and the lower redistribution structure(upper130/lower130) in the vertical direction, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose wherein a distance between the signal pad(upper110/lower110) and the lower redistribution structure(upper130/lower130) in a vertical direction is less than a distance between the power pad and the lower redistribution structure(upper130/lower130) in the vertical direction as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize the reliability and durability of semiconductor packages [0003, Chung]. See MPEP 2144.05.
Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Re claim 2 Hong and Chung disclose the semiconductor package of claim 1, wherein the distance between the signal pad(upper110/lower110) and the lower redistribution structure(upper130/lower130) in the vertical direction is identical to a distance between the grounding plane and the lower redistribution structure(upper130/lower130) in the vertical direction.
Re claim 3 Hong and Chung disclose the semiconductor package of claim 2, wherein: the upper redistribution structure(upper130/lower130) further comprises a signal line pattern electrically connected to the signal pad(upper110/lower110), a distance between the signal line pattern and the lower redistribution structure(upper130/lower130) in the vertical direction is identical to the distance between the signal pad(upper110/lower110) and the lower redistribution structure(upper130/lower130) in the vertical direction, and a width of the signal pad(upper110/lower110) in a horizontal direction is from about 10 times to about 30 times greater than a width of the signal line pattern in the horizontal direction, the horizontal direction intersecting the vertical direction.
Re claim 4 Hong and Chung disclose the semiconductor package of claim 2, wherein: a distance between the signal pad(upper110/lower110) and a bottom surface of the upper insulation layer(ILD1/ILD2/ILD4) in the vertical direction by about 10 μm to about 50 μm, and a distance between the power pad and a top surface of the upper insulation layer(ILD1/ILD2/ILD4) in the vertical direction by about 10 μm to about 50 μm.
Re claim 5 Hong and Chung disclose the semiconductor package of claim 1, further comprising: a molding layer(9) on the lower redistribution structure(upper130/lower130) and at least partially surrounding the lower semiconductor chip(IC1/IC2); and a via electrode(V1-V3) extending into the molding layer(9) and electrically connecting the lower redistribution structure(upper130/lower130) to the upper redistribution structure(upper130/lower130), wherein the upper redistribution structure(upper130/lower130) comprises a first upper redistribution layer contacting the molding layer(9) and the via electrode(V1-V3) and a second upper redistribution layer on the first upper redistribution layer, the first upper redistribution layer comprises the signal pad(upper110/lower110) and the grounding plane, and the second upper redistribution layer comprises the power pad.
Re claim 6 Hong and Chung disclose the semiconductor package of claim 1, further comprising: a molding layer(9) on the lower redistribution structure(upper130/lower130) and at least partially surrounding the lower semiconductor chip(IC1/IC2); and a via electrode(V1-V3) extending into the molding layer(9) and electrically connecting the lower redistribution structure(upper130/lower130) to the upper redistribution structure(upper130/lower130), wherein the upper redistribution structure(upper130/lower130) comprises a first upper redistribution layer that contacts the molding layer(9) and the via electrode(V1-V3), a second upper redistribution layer on the first upper redistribution layer, and a third upper redistribution layer on the second upper redistribution layer, the first upper redistribution layer comprises the signal pad(upper110/lower110), the second upper redistribution layer comprises the grounding plane, and the third upper redistribution layer comprises the power pad.
Re claim 7 Hong and Chung disclose the semiconductor package of claim 1, wherein: the upper redistribution structure(upper130/lower130) comprises a first groove, a second groove, and a third groove, the first groove extends from a top surface of the upper insulation layer(ILD1/ILD2/ILD4) toward the grounding plane, the second groove extends from the top surface of the upper insulation layer(ILD1/ILD2/ILD4) toward the signal pad(upper110/lower110), and the third groove extends from the top surface of the upper insulation layer(ILD1/ILD2/ILD4) toward the power pad.
Re claim 8 Hong and Chung disclose the semiconductor package of claim 7,.
Although the combination of Hong and Chung do not disclose wherein a depth of the third groove in the vertical direction is less than a depth of the first groove and a depth of the second groove in the vertical direction, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose wherein a depth of the third groove in the vertical direction is less than a depth of the first groove and a depth of the second groove in the vertical direction as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize the reliability and durability of semiconductor packages [0003, Chung]. See MPEP 2144.05.
Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Re claim 9 Hong and Chung disclose the semiconductor package of claim 7,.
Although the combination of Hong and Chung do not disclose wherein a depth of the first groove in the vertical direction is identical to a depth of the second groove in the vertical direction, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose wherein a depth of the first groove in the vertical direction is identical to a depth of the second groove in the vertical direction as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize the reliability and durability of semiconductor packages [0003, Chung]. See MPEP 2144.05.
Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Re claim 10 Hong and Chung disclose the semiconductor package of claim 1, further comprising: an upper semiconductor chip(IC1/IC2) on the upper redistribution structure(upper130/lower130); and a plurality of connection terminals between the upper semiconductor chip(IC1/IC2) and the upper redistribution structure(upper130/lower130).
Re claim 11 Hong and Chung disclose the semiconductor package of claim 10, wherein: the plurality of connection terminals comprise a first connection terminal, a second connection terminal, and a third connection terminal, the first connection terminal extends into an upper portion of the upper insulation layer(ILD1/ILD2/ILD4) and is electrically connected to the grounding plane, the second connection terminal extends into the upper portion of the upper insulation layer(ILD1/ILD2/ILD4) and is electrically connected to the signal pad(upper110/lower110), the third connection terminal extends into the upper portion of the upper insulation layer(ILD1/ILD2/ILD4) and is electrically connected to the power pad, and a height of the third connection terminal in the vertical direction is less than a height of the first connection terminal in the vertical direction.
Re claim 12 Hong and Chung disclose the semiconductor package of claim 11,.
Although the combination of Hong and Chung do not disclose wherein the height of the third connection terminal in the vertical direction is identical to a height of the second connection terminal in the vertical direction, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose wherein the height of the third connection terminal in the vertical direction is identical to a height of the second connection terminal in the vertical direction as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize the reliability and durability of semiconductor packages [0003, Chung]. See MPEP 2144.05.
Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Re claim 13 Hong discloses a semiconductor package comprising: a lower redistribution structure(upper130/lower130); a lower semiconductor chip(IC1/IC2) on the lower redistribution structure(upper130/lower130); and an upper redistribution structure(upper130/lower130) on the lower semiconductor chip(IC1/IC2) and comprising a signal redistribution pattern(upper130/lower130), and an upper insulation layer(ILD1/ILD2/ILD4), wherein the upper redistribution structure(upper130/lower130) comprises a plurality of redistribution layers(upper130/lower130), wherein a first upper redistribution layer of the plurality of redistribution layers comprises a first region and a second region, wherein the grounding plane is in the first region, and wherein a signal pad(upper110/lower110) of the signal redistribution pattern(upper130/lower130) is on the second region.
Hong does not disclose an upper redistribution structure(upper130/lower130) on the lower semiconductor chip(IC1/IC2) and comprising a signal redistribution pattern(upper130/lower130), a power pad, a grounding plane, and an upper insulation layer(ILD1/ILD2/ILD4), wherein the upper redistribution structure(upper130/lower130) comprises a plurality of redistribution layers, wherein a first upper redistribution layer of the plurality of redistribution layers comprises a first region and a second region, wherein the grounding plane is in the first region, and wherein a signal pad(upper110/lower110) of the signal redistribution pattern(upper130/lower130) is on the second region.
Chung disclose a semiconductor chip and comprising a signal pad(IO of Chung), a power pad(VP1/VP2 of Chung), a grounding plane since the ground is straight to or aligned with ground this may be interpreted as a plane)[0020 of Chung], and an upper insulation layer(ILD1/ILD2/ILD4),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chung to the teachings of Hong in order to improve reliability and durability of semiconductor packages [0003, Chung]. In doing so, an upper redistribution structure(upper130/lower130) on the lower semiconductor chip(IC1/IC2) and comprising a signal pad(IO of Chung), a power pad(VP1/VP2 of Chung), a grounding plane since the ground is straight to or aligned with ground this may be interpreted as a plane)[0020 of Chung], and an upper insulation layer(ILD1/ILD2/ILD4), wherein the signal pad(upper110/lower110), the power pad(VP1/VP2 of Chung), and the grounding plane since the ground is straight to or aligned with ground this may be interpreted as a plane)[0020 of Chung] are in the upper insulation layer(241/242/250 of Chung),
Although the combination of Hong and Chung do not disclose wherein a distance between the signal pad(upper110/lower110) and the lower redistribution structure(upper130/lower130) in a vertical direction is less than a distance between the power pad(VP1/VP2 of Chung) and the lower redistribution structure(upper130/lower130) in the vertical direction, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose wherein a distance between the signal pad(upper110/lower110) and the lower redistribution structure(upper130/lower130) in a vertical direction is less than a distance between the power pad(VP1/VP2 of Chung) and the lower redistribution structure(upper130/lower130) in the vertical direction as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize the reliability and durability of semiconductor packages [0003, Chung]. See MPEP 2144.05.
Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Re claim 14 Hong and Chung disclose the semiconductor package of claim 13, wherein: the signal redistribution pattern(upper130/lower130) comprises a signal line pattern, a distance between the signal pad(upper110/lower110) and the lower redistribution structure(upper130/lower130) in a vertical direction is greater than a distance between the signal line pattern and the lower redistribution structure(upper130/lower130) in the vertical direction, the vertical direction is perpendicular to an upper surface of the lower redistribution structure(upper130/lower130), and the signal redistribution pattern(upper130/lower130) comprises a signal via pattern electrically connecting the signal pad(upper110/lower110) to the signal line pattern.
Re claim 15 Hong and Chung disclose the semiconductor package of claim 14, wherein the distance between the signal line pattern and the lower redistribution structure(upper130/lower130) in the vertical direction is less than or equal to a distance between the grounding plane and the lower redistribution structure(upper130/lower130) in the vertical direction.
Re claim 16 Hong and Chung disclose the semiconductor package of claim 14, wherein: a bottom surface of the signal pad(upper110/lower110) is electrically connected to the signal via pattern, and the signal pad(upper110/lower110) at least partially overlaps the signal line pattern in the vertical direction.
Re claim 17 Hong and Chung disclose the semiconductor package of claim 13, wherein the signal pad(upper110/lower110) and the power pad are on a second upper redistribution layer of the plurality of redistribution layers, and wherein the second upper redistribution layer is on the first upper redistribution layer.
Re claim 18 Hong discloses a semiconductor package comprising: a lower redistribution structure(upper130/lower130); a lower semiconductor chip(IC1/IC2) on the lower redistribution structure(upper130/lower130); a molding layer(9) on the lower redistribution structure(upper130/lower130) and at least partially surrounding the lower semiconductor chip(IC1/IC2); an upper redistribution structure(upper130/lower130) on the molding layer(9) and comprising a signal pad(upper110/lower110), and an upper insulation layer(ILD1/ILD2/ILD4); a via electrode(V1-V3) extending into the molding layer(9) and electrically connecting the lower redistribution structure(upper130/lower130) to the upper redistribution structure(upper130/lower130); and an upper semiconductor chip(IC1/IC2) on the upper redistribution structure(upper130/lower130), and wherein the vertical direction is perpendicular to an upper surface of the lower redistribution structure(upper130/lower130).
Hong does not discloses an upper redistribution structure(upper130/lower130) on the molding layer(9) and comprising a signal pad(upper110/lower110), a power pad, a grounding plane, and an upper insulation layer(ILD1/ILD2/ILD4); and an upper semiconductor chip(IC1/IC2) on the upper redistribution structure(upper130/lower130), wherein the signal pad(upper110/lower110), the power pad, and the grounding plane are in the upper insulation layer(ILD1/ILD2/ILD4), wherein a distance between the signal pad(upper110/lower110) and the lower redistribution structure(upper130/lower130) in a vertical direction is identical to a distance between the grounding plane and the lower redistribution structure(upper130/lower130) in the vertical direction,
Chung disclose discloses an upper redistribution structure(200 of Chung) comprising a signal pad(IO of Chung), a power pad(VP1/VP2 of Chung), a grounding plane(since the ground is straight to or aligned with ground this may be interpreted as a plane)[0020 of Chung],
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chung to the teachings of Hong in order to improve reliability and durability of semiconductor packages [0003, Chung]. In doing so, an upper redistribution structure(upper130/lower130) on the molding layer(9) and comprising a signal pad(IO of Chung), a power pad(VP1/VP2 of Chung), a grounding plane(since the ground is straight to or aligned with ground this may be interpreted as a plane)[0020 of Chung], and an upper insulation layer(ILD1/ILD2/ILD4); and an upper semiconductor chip(IC1/IC2) on the upper redistribution structure(upper130/lower130), wherein the signal pad(upper110/lower110), the power pad(VP1/VP2 of Chung), and the grounding plane(since the ground is straight to or aligned with ground this may be interpreted as a plane)[0020 of Chung] are in the upper insulation layer(ILD1/ILD2/ILD4),
Although the combination of Hong and Chung do not disclose wherein a distance between the signal pad(upper110/lower110) and the lower redistribution structure(upper130/lower130) in a vertical direction is identical to a distance between the grounding plane and the lower redistribution structure(upper130/lower130) in the vertical direction, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose wherein a distance between the signal pad(upper110/lower110) and the lower redistribution structure(upper130/lower130) in a vertical direction is identical to a distance between the grounding plane and the lower redistribution structure(upper130/lower130) in the vertical direction as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize the reliability and durability of semiconductor packages [0003, Chung]. See MPEP 2144.05.
Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Re claim 19 Hong and Chung disclose the semiconductor package of claim 18, wherein the upper insulation layer(ILD1/ILD2/ILD4) is between the signal pad(upper110/lower110) and the power pad.
Re claim 20 Hong and Chung disclose the semiconductor package of claim 18, wherein: the upper redistribution structure(upper130/lower130) further comprises a signal line pattern that is electrically connected to the signal pad(upper110/lower110), a distance between the signal line pattern and the lower redistribution structure(upper130/lower130) in the vertical direction is identical to the distance between the signal pad(upper110/lower110) and the lower redistribution structure(upper130/lower130) in the vertical direction, and the grounding plane is spaced apart from the signal line pattern and the signal pad(upper110/lower110) in a horizontal direction that intersects the vertical direction.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
