DETAILED ACTION
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
2. Claim 1 is objected to because of the following informalities:
In claim 1, line 12, “an insulating layer provided between the respective wiring layers” should be changed to “an insulating layer respectively provided between the first and second wiring layers”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 1 – 9, 14 - 16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang et al. (20230420429).
With regard to claim 1, Chang et al. disclose a semiconductor device comprising:
first and second semiconductor chips (referred to as “405A” and “405B” by examiner’s annotation shown in fig. 16 below; wherein the first and second semiconductor chips 405A, 405B made from the silicon structures 405 and wherein the silicon structure 405A, 405B include a silicon substrate 410, as thinned and diced provided separately from each other, functions as first and second semiconductor chips; for example, see paragraph [0034]);
each semiconductor chip including a first main electrode (referred to as “498A” by examiner’s annotation shown in fig. 16 below; wherein the first main electrode 498A made from the metal structure 498) on a top surface side and a second main electrode (referred to as “408A” by examiner’s annotation shown in fig. 16 below; wherein the second main electrode 408A made from the conductive structure 408) on a bottom surface side; and
a printed circuit board (a printed circuit board 100; or an interposer structures 400, 500 forming in a printed circuit board 100, functions as a printed circuit board) provided at a circumference of the first and second semiconductor chips (405A, 405B), the printed circuit board including a plurality of wiring layers (474, 580) including a first wiring layer (referred to as “580A” by examiner’s annotation shown in fig. 16 below; wherein the first wiring layers 580A made from the wiring layer 580) which is an uppermost layer (500) electrically connected to the first main electrode (498A) of the first semiconductor chip (405A) through a connection member (referred to as “498B” by examiner’s annotation shown in fig. 16 below), and
a second wiring layer (referred to as “474A” by examiner’s annotation shown in fig. 16 below) which is a lowermost layer (a lowermost layer having die-side redistribution dielectric layers 472) electrically connected to the first wiring layer (580A) through a via (486) and further to the second main electrode (408A) of the second semiconductor chip (405B), and an insulating layer (490, 472) provided between the respective wiring layers (580A, 474A).
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With regard to claim 2, Chang et al. disclose the connection member (498B) is a bonding wire.
With regard to claim 3, Chang et al. disclose an external connection terminal (180) electrically connected to the first wiring layer (580A).
With regard to claim 4, Chang et al. disclose the plural wiring layers further include a third wiring layer (referred to as “580C” by examiner’s annotation shown in fig. 16 below; wherein the first wiring layers 580C made from the wiring layer 580) which is the uppermost layer (500) provided separately from the first wiring layer (580A) and electrically connected to the first main electrode (498A) of the second semiconductor chip (405B) through a connection member (referred to as “498C” by examiner’s annotation shown in fig. 16 below).
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1083
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With regard to claim 5, Chang et al. disclose an external connection terminal (180) electrically connected to the third wiring layer (580C).
With regard to claim 6, Chang et al. disclose the plural wiring layers further include: a third wiring layer (referred to as “474C” by examiner’s annotation shown in fig. 16 below; wherein the third wiring layers 474C made from the wiring layer 474) which is the lowermost layer provided separately from the second wiring layer (474A) and electrically connected to the second main electrode of the first semiconductor chip (405B); and a fourth wiring layer (referred to as “580D” by examiner’s annotation shown in fig. 16 below; wherein the fourth wiring layer 580D are made from the wiring layer 580) which is the uppermost layer (500) provided separately from the first wiring layer (580A) and electrically connected to the third wiring layer (474C) through a via (486).
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With regard to claim 7, Chang et al. disclose an external connection terminal (180) electrically connected to the fourth wiring layer (580D).
With regard to claim 8, Chang et al. disclose the first semiconductor chip further includes a control electrode (bonding interconnection pads 588 functions as a control electrode) on the top surface side; and the plural wiring layers further include a third wiring layer (referred to as “580C” by examiner’s annotation shown in fig. 16 below; wherein the third wiring layer 580C are made from the wiring layer 580) which is the uppermost layer (500) provided separately from the first wiring layer (580A) and electrically connected to the control electrode (588) of the first semiconductor chip (405A) through a connection member (referred to as “498C” by examiner’s annotation shown in fig. 16 below), a fourth wiring layer (referred to as “474D” by examiner’s annotation shown in fig. 16 below; wherein the fourth wiring layer 474D are made from the wiring layer 474) provided as a lower layer than the third wiring layer (580C) and electrically connected to the third wiring layer (580C) through a via (486), and a fifth wiring layer (referred to as “580E” by examiner’s annotation shown in fig. 16 below; wherein the fifth wiring layer 580E are made from the wiring layer 580) which is the uppermost layer (500) provided separately from each of the first wiring layer (580A) and the third wiring layer (580C) and electrically connected to the fourth wiring layer (474D) through a via (486).
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With regard to claim 9, Chang et al. disclose a first control terminal (180) electrically connected to the fifth wiring layer (580E).
With regard to claim 14, Chang et al. disclose the printed circuit board is provided with a first opening (referred to as “OP1” by examiner’s annotation shown in fig. 16 below) surrounding the first semiconductor chip (405A) and a second opening (referred to as “OP2” by examiner’s annotation shown in fig. 16 below) surrounding the second semiconductor chip (405B).
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With regard to claim 15, Chang et al. disclose an insulated circuit substrate including: an insulating substrate (referred to as “SB” by examiner’s annotation shown in fig. 16 below); a first circuit plate (one of conductive layers 478 functions as a first circuit plate) and a second circuit plate (one of conductive layers 478 functions as a second circuit plate) provided separately from each other on a top surface side of the insulating substrate (SB); and a heat-releasing plate (solder material portions 790 functions as a heat-releasing plate) provided on a bottom surface side of the insulating substrate (SB), wherein the first semiconductor chip (405A) is provided on the first circuit plate (one of conductive layers 478 functions as a first circuit plate), and the second semiconductor chip (405B) is provided on the second circuit plate (one of conductive layers 478 functions as a second circuit plate).
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568
885
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With regard to claim 16, Chang et al. disclose the plural wiring layers further include a third wiring layer (referred to as “474C” by examiner’s annotation shown in fig. 16 below) which is the lowermost layer provided separately from the second wiring layer (474A) and electrically connected to the second main electrode (408A) of the first semiconductor chip (405A); the second wiring layer (474A) and the third wiring layer (474C) each have a top surface partly exposed on the insulating layer (472); the first semiconductor chip (405A) is provided on the exposed top surface of the third wiring layer (474C); and the second semiconductor chip (405B) is provided on the exposed top surface of the second wiring layer (474A).
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Allowable Subject Matter
5. Claims 10 - 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 10 - 13 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the plural wiring layers further include: a sixth wiring layer which is the uppermost layer provided separately from each of the first wiring layer, the third wiring layer, and the fifth wiring layer and electrically connected to the first main electrode of the first semiconductor chip through a connection member; a seventh wiring layer provided as a lower layer than the fourth wiring layer and electrically connected to the sixth wiring layer through a via; and an eighth wiring layer which is the uppermost layer provided separately from each of the first wiring layer, the third wiring layer, the fifth wiring layer, and the sixth wiring layer and electrically connected to the seventh wiring layer through a via as recited in claim 10.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights