DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed January 06, 2026 is acknowledged. Claims 1, 4, 8, 11-12, 16 and 20 have been amended. Claims 1-20 are pending.
Action on merits of claims 1-20 follows.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There does not appear to be a written description of the claim limitation “a p-type region(s) and an n-type region each having a top surface in contact with bottoms of at least three of the plurality of trenches” (amended claims 1 and 20) (emphasis added) and “each of the plurality of n-type regions having a top surface so as to be in contact with the bottoms of the plurality of trenches” (amended claim 16) (emphasis added) in the application as filed.
Applicant must cancel the un-support new matters in response to the Office Action.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Amended Claim 1, lines 5-6, recites: “a p-type region and an n-type region each having a top surface in contact with bottoms of at least three of the plurality of trenches”.
and, lines 8-10, recites: “the top surface of the p-type region being positioned farther from the base layer than is a position of the top surface of the n-type region in a thickness direction of the base layer”
Two limitations are contradictory.
The first limitation: “a p-type region and an n-type region each having a top surface in contact with bottoms of at least three of the plurality of trenches” means the top surface of both n-type and p-type are at the same position.
The second limitation: “the top surface of the p-type region being positioned farther from the base layer than is a position of the top surface of the n-type region in a thickness direction of the base layer” means the top surface of the n-type and the p-type are at different positions.
Two limitations of claim 1 are contradictory.
Therefore, claim 1 and all dependent claims are indefinite.
Amended claims 16 and 20 recite similar limitations.
Therefore, claims 16, 20 and all dependent claims are indefinite.
Regarding Claim 19, claim 19, lines 4-7, recites: “a bottom surface of the base layer is in contact with one of the plurality of n-type regions in one of the plurality of unit cells and “the bottom surface of the base layer is in contact with the one of the plurality of p-type regions in another one of the plurality of unit cells”.
The limitations above claimed that both n-type region and p-type region are in contact with the bottom surface of the base layer.
The above limitations of claim 19, contravenes the limitation of the amended independent claim 16.
The amended independent Claim 16 recites: “the top surface of at least one of the plurality of p-type regions being located farther from the base layer than are positions of the top surfaces of the plurality of n-type regions in a thickness direction of the base layer”
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-12 and 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YAMAMOTO et al. (US. Pub. No. 2014/0175459).
With respect to claim 1, As best understood by the Examiner, YAMAMOTO teaches a trench-type power semiconductor device substantially as claimed , including:
an n-type drift layer (2);
a p-type base layer (3) provided above the drift layer (2);
a plurality of trenches (6) penetrating through the base layer (3); and
a p-type region (10a); and an n-type region (2a) each having a top surface in contact with bottoms of at least three (not shown) of the plurality of trenches;
wherein the n-type region (2a) has an impurity concentration (n) higher than an impurity concentration (n-) of the drift layer (2), the top surface of the p-type region (10a) being positioned farther from the base layer (3) than is a position of the top surface of the n-type region (2a) in a thickness direction of the base layer. (See FIGs. 12-13).
Regarding the limitations: “plurality of trenches” and “at least three of the plurality of trenches”, the power device of YAMAMOTO includes a plurality of trenches, i.e., two or more trench gate structures are arranged in parallel along the x direction.
With respect to claim 2, each of the plurality of trenches (6) of YAMAMOTO has a striped planar pattern.
With respect to claim 3, the p-type region (10a) of YAMAMOTO has an impurity concentration higher than an impurity concentration of the base layer (3).
With respect to claim 4, the p-type region (10a) of YAMAMOTO is provided in plurality, the plurality of trenches (6) extend in parallel with each other, and the plurality of p-type regions (10a) each have a stripe shape and are provided side by side successively in a longitudinal direction of the plurality of trenches (6) in which the plurality of trenches (6) each extend.
With respect to claim 5, the power semiconductor device of YAMAMOTO further comprises a plurality of unit cells, wherein one of the plurality of unit cells includes one of the plurality of p-type regions (5) that is apart from the base layer (3).
With respect to claim 6, the one of the plurality of unit cells of YAMAMOTO includes the n-type region (2a), the n-type region (2a) being provided between the one of the plurality of p-type regions (10a) and the base layer (3).
With respect to claim 7, bottom surfaces of the plurality of p-type regions (10a) of YAMAMOTO are in contact with the drift layer (2).
With respect to claim 8, the n-type region (2a) of YAMAMOTO is provided in plurality, the plurality of trenches (6) extend in parallel with each other, and the plurality of n-type regions (2a) each have a stripe shape and are provided side by side successively in a longitudinal direction of the plurality of trenches (6) in which the plurality of trenches each extend.
With respect to claim 9, the power semiconductor device of YAMAMOTO further comprises a plurality of unit cells, wherein one of the plurality of unit cells includes one of the plurality of n-type regions (2a) that is in contact with a bottom, and a portion of a side wall, of one of the plurality of trenches (6).
With respect to claim 10, bottom surfaces of the plurality of n-type regions (2a) of YAMAMOTO are in contact with the drift layer (2).
With respect to claim 11, top surfaces of the plurality of n-type regions (2a) of YAMAMOTO are in contact with the base layer (3).
With respect to claim 12, the plurality of trenches (6) of YAMAMOTO extend in parallel with each other and the p-type region (10a) is provided in plurality, and the plurality of p-type regions (10a) and the n-type region (2a) are provided such that one of the plurality of p-type regions (10) and the n-type region (2a) alternate in a direction (y) in which the plurality of trenches (6) extend.
With respect to claim 14, the power semiconductor device of YAMAMOTO is a silicon carbide semiconductor device.
With respect to claim 15, the power semiconductor device of YAMAMOTO is a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT).
With respect to claim 16, As best understood by the Examiner, YMAMAOTO teaches a trench-type power semiconductor device, as claimed including:
an n-type drift layer (2);
a p-type base layer (3) provided above the drift layer (2);
a plurality of trenches (6) penetrating through the base layer (3) and extending in parallel with each other (see claim 1 above);
a plurality of p-type regions (10a) each having a stripe shape and extending in a width direction (y) of the plurality of trenches (6), each of the plurality of p-type regions (10a) having a top surface so as to be in contact with bottoms of the trenches (6); and
each of a plurality of n-type regions (2a) each having a stripe shape and extending in the width direction of the plurality of trenches (6), each of the plurality of n-type regions (2a) having a top surface so as to be in contact with the bottoms of the plurality of trenches (6), the plurality of n-type regions (2a) having an impurity concentration (n) higher than an impurity concentration (n-) of the drift layer (2), the top surface of at least one of the plurality of p-type regions (2a) being located farther from the base layer (3) than are positions of the top surfaces of the plurality of n-type regions (2a) in a thickness direction of the base layer (3). (See FIGs. 12-13).
With respect to claim 17, at least one of the plurality of p-type regions (10a) of YAMAMOTO is in contact with a bottom, and a portion of a side wall, of at least one of the plurality of trenches (6).
With respect to claim 18, each of the plurality of n-type regions (2a) of YAMAMOTO is in contact with bottoms, and portions of side walls, of the plurality of trenches (6).
With respect to claim 19, As best understood by the Examiner, the power semiconductor device of YAMAMOTO further comprises a plurality of unit cells, wherein in a cross section in the width direction, where one of the plurality of p-type regions (10a) is in contact with bottoms of at least three of the trenches (6), a bottom surface of the base layer (3) is in contact with one of the plurality of n-type regions (2a) in one of the plurality of unit cells and the bottom surface of the base layer (3) is in contact with the one of the plurality of p-type regions (10) in another one of the plurality of unit cells.
With respect to claim 20, As best understood by the Examiner, YAMAMOTO teaches a trench-type power semiconductor device having a plurality of unit cells, as claimed including:
an n-type drift layer (2);
a p-type base layer (3) provided above the drift layer (2);
a plurality of trenches (6) penetrating through the base layer (3) and extending in parallel with each other (see claim 1 above); and
a plurality of p-type regions (10a) and an n-type region (2a) each having a top surface in contact with bottoms of at least three of the plurality of trenches (see claim 1 above), wherein the n-type region (2a) has an impurity concentration (n) higher than an impurity concentration (n-) of the drift layer (2), and
in a cross section passing through the plurality of p-type regions (10a) in a width direction (y) of the plurality of trenches (6), the bottom surface of the base layer (3) is in contact with the top surface of the n-type region (2a) in one of the plurality of unit cells, and the bottom surface of the base layer (3) is in contact with the top surface of a corresponding one of the plurality of p-type regions (10b) in another one of the plurality of unit cells, the top surface of at least one of the plurality of p-type regions (10a) being positioned farther from the base layer (3) than is a position of the top surface of the n-type region (2a) in a thickness direction of the base layer. (See Figs. 12-13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO ‘459 as applied to claim 1 above, and further in view of NAKAMURA (US. Pub. No. 2014/0141585) of record.
YAMAMOTO teaches the power semiconductor device as described in claim 1 above including: a plurality of unit cells having a cell pitch.
Thus, YAMAMOTO is shown to teach all the features of the claim with the exception of explicitly disclosing the cell pitch of less than 4.0 μm.
However, NAKAMURA teaches a power semiconductor device including: a plurality of unit cells, having a cell pitch of 2 µm, hence less than 4.0 μm.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the power semiconductor device of YAMAMOTO having the cell pitch of less than 4 µm as taught by NAKAMURA to achieve high channel density.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/Primary Examiner, Art Unit 2893