333Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6-9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Gogoi [US PGPUB 20090108403] in view Hosogai et al. [US PGUB 20220028782] (hereinafter Hosogai).
Regarding claim 1, Gogoi teaches a method of fabricating a unit cell of a focal plane array, the method comprising:
providing an integrated circuit substrate (110, Para 33) including one or more integrated electrical components (transistors, Para 33);
depositing a proximal portion of a dielectric layer (104, Para 71) on the integrated circuit substrate (Fig. 7);
etching a plurality of recess structures (712, Para 71) into the proximal portion of the dielectric layer (Fig. 7), wherein each of the plurality of recess structures defines a partial via formed in a first surface of the proximal portion of the dielectric layer and includes sidewalls that extend from the first surface to a bottom portion of the respective recess structure (Fig. 7);
forming a capacitor structure (150(750/755/760), Para 84/90) in the plurality of recess structures (Fig. 10);
depositing a distal portion of the dielectric layer (1180, Para 97) on the capacitor structure and a region of the proximal portion of the dielectric layer (Fig. 12);
forming a plurality of vias (portion of 300/301 in trench 1184/1186, Para 47, Fig. 1/12) passing through the distal portion of the dielectric layer to the capacitor structure (Fig. 12);
forming a metal layer (portion of 300/301 outside of trench 1184/1186, Para 100) on the distal portion of the dielectric layer (Fig. 1/12), wherein the plurality of vias are positioned between the capacitor structure and the metal layer and electrically connect the capacitor structure to the metal layer (Fig. 1, Para 99/100).
Gogoi does not specifically disclose forming a detector overlying the metal layer.
However, it is noted that Gogoi discloses that passive components such as capacitors may be integrated in applications, such as digital, analog, RF or mixed signal circuits. Thus, a person having ordinary skills in the art before the effective filing date of the claimed invention will find it at least obvious to implement the semiconductor structure (taught by Gogoi) comprising the capacitor structure in an imaging device.
Referring to the invention of Hosogai, Hosogai discloses implementing a semiconductor structure comprising the capacitor structure in an imaging unit wherein an image sensor 30 (detector) is formed above capacitor structure of the device (Para 30, Fig. 6).
In view of such teaching by Hosogai, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Gogoi comprise a detector formed above the semiconductor structure at least based on the rationale of relying on teachings, suggestions, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention (MPEP 2143.I.G) or combining prior art elements according to known methods to yield predictable results (MPEP 2143.I.A).
Regarding claim 2, Gogoi teaches a method wherein forming the capacitor structure in the plurality of recess structures comprises:
depositing a first electrode layer (750, Para 34) over the plurality of recess structures (Fig. 8);
depositing a capacitor dielectric material (755, Para 34) over the first electrode layer (Fig. 8); and
depositing a second electrode layer (760, Para 34) over the capacitor dielectric material (Fig. 8).
Regarding claim 4, Gogoi teaches a method wherein the capacitor dielectric material comprises a metal oxide, a metal nitride, or a metal oxynitride (Para 87).
Regarding claim 6, Gogoi teaches a method wherein forming the plurality of vias passing through the distal portion of the dielectric layer to the capacitor structure comprises electrically connecting the second electrode layer of the capacitor structure to the metal layer (Fig. 12).
Regarding claim 7, Gogoi teaches a method wherein the distal portion of the dielectric layer fully isolates regions below and above the capacitor structure (Fig. 12).
Regarding claim 8, the modified invention of Gogoi teaches the limitation of claim 1 upon which it depends.
The modified invention of Gogoi does not specifically disclose a method further comprising depositing an interlayer dielectric over the metal layer prior to forming the detector.
However, referring to Fig. 4, it is noted that the detector is connected to the semiconductor device via exposed terminals 21/23/32/33. However, a person having ordinary skills in the art understand that the exposed terminal are prone to short-circuiting, thus it would be found obvious to have an interlayer dielectric over the metal layer prior to forming the detector.
Regarding claim 9, the modified invention of Gogoi teaches a method wherein the distal portion of the dielectric layer is positioned between the integrated circuit substrate and the detector (Gogoi, Fig. 1, in view of the detector being connected to metal 300/301, based on Hosogai’s disclosure).
Regarding claim 13, Gogoi teaches the limitation of claim 1 upon which it depends.
Gogoi does not specifically disclose a method further comprising:
etching a second plurality of recess structures into the proximal portion of the dielectric layer;
forming a second capacitor structure in the second plurality of recess structures;
depositing the distal portion of the dielectric layer on the second capacitor structure;
forming a second plurality of vias passing through the distal portion of the dielectric layer to the second capacitor structure; and
forming a second metal layer on the distal portion of the dielectric layer.
Referring to Fig. 4 of Hosogai’s invention, Hosogai teaches a semiconductor device with dual (mirrored) capacitor structure.
In view of such teaching by Hosogai, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Gogoi comprising a second capacitor structure (as taught by Hosogai) which would be obviously formed as the claimed since the method of forming the second capacitor structure is similar to that of the first capacitor structure. Such obviousness would result in increase in storage capability of the device.
Allowable Subject Matter
Claims 3, 5, 10-12, and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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