DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Burger et al. (US Pub.: 2017/0147624) in view of Spry et al. (US Patent 9,910,814) and Isenegger (US Patent 11,593,024).
As per claim 1, Burger teaches/suggests a device for implementing a storage architecture, comprising: a front-end chip including at least one front-end link (e.g. associated with front end processor being implemented on FPGA/ASIC: [0019]; [0035]-[0038]; [0046]; and [0128]-[0129]), and at least one back-end chip including back-end link for communication with the front-end link (e.g. associated with back end processor being implemented on FPGA/ASIC, wherein back end processor communicated with front end processor: [0019]; [0035]-[0038]; [0046]-[0056]; and [0128]-[0129]), wherein the front-end link and the back-end link operating accordingly, respectively, wherein a data packet that is transmitted between the front-end link and the back-end link (e.g. associated with communication of packet between front end processor and back end processor: [0050]; [0054]) (Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; and [0128]-[0129]).
Burger does not teach the device comprising:
includes a link layer and a physical layer,
data is composed of at least one flow control digit,
wherein the flow control digit is composed of at least one physical digit,
wherein the link layer is configured to process data in a form of separating the flow control digit into upper layer data and flow control data, and
wherein the physical layer is configured to process data in the form of a data packet part and a control packet part.
Spry teaches/suggests a device comprising: includes a link layer (e.g. associated with LL (132/152) in Fig. 1: col. 2, ll. 4-24) and a physical layer (e.g. associated with PHY (134/154) in Fig. 1: col. 2, ll. 4-24), data is composed of at least one flow control, wherein the flow control operates accordingly (e.g. equivocate to communicating data composed of flow control packets: col. 3, l. 66 to col. 4, l. 4), wherein the link layer is configured to process data in a form of separating the flow control into upper layer data and flow control data (e.g. associated with data and flow control being communicated between Link Layers (132 and 152) in Fig. 1: col. 3, l. 33 to col. 4, l. 8), and wherein the physical layer is configured to process data in the form of a data packet part and a control packet part (e.g. associated with data and flow control being communicated between Link Layers (LL) (132 and 152) via corresponding physical Layers (PHY) (134 and 154) in Fig. 1: col. 3, l. 33 to col. 4, l. 8) (Fig. 1; and col. 2, l. 1 to col. 5, l. 31).
Isenegger teaches/suggests a device comprising: flow control digit (e.g. associated credit/digit for credit based data communication: col. 1, l. 61 to col. 2, l. 6), wherein the flow control digit is composed of at least one physical digit (e.g. associated with credit being representation of buffer/physical space: col. 7, ll. 8-25), operating with the flow control digit (col. 1, l. 61 to col. 2, l. 49; and col. 6, l. 12 to col. 10, l. 8).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Spry’s protocol stack and Isenegger’s credit based communication into Burger’s device for the benefit of providing efficient communication between integrated circuit chips (Spry, col. 2, ll. 1-3), and better utilization of resources (Isenegger, col. 7, ll. 50-514) to obtain the invention as specified in claim 1.
As per claim 2, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 1 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the upper layer data is configured in a table form in which a row is composed of "J" bits and a column is composed of "W" bits, and wherein "J" is a natural number and "W" is a natural number (e.g. functionally equating to the proper communication of bits of data between front end and back end) (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8).
As per claim 3, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 2 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the flow control data is configured in a table form in which a row is composed of 1 bit and a column is composed of "]" bits (e.g. functionally equating to the proper implementation of credit base communication of bits of data between front end and back end) (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8).
As per claim 4, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 3 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the flow control data indicates whether an idle state and which message the upper layer data corresponds to (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; col. 7, ll. 42-46; col. 8, ll. 55-59; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features for IDLE state.
As per claim 5, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 3 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the control packet part has a same number of bits of data length as the data packet part (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as data is communicated between front end and back end.
As per claim 6, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 5 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the control packet part and the data packet part have a data length of "J" bits, respectively (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as data is communicated between front end and back end.
As per claim 7, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 6 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the control packet part has one data width, and wherein the data packet part has "W" data widths (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as data is communicated between front end and back end.
As per claim 8, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 3 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the physical digit has a size of "W+1" bits including a 1-bit control packet part and a "W"-bit data packet part (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as data is communicated between front end and back end.
As per claim 9, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 8 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the flow control digit has a size of "J+(WxJ)" bits including a "J"-bit control packet part and a "WxJ"-bit data packet part (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as data is communicated between front end and back end.
As per claim 10, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 1 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the link layer of the front-end link is configured to receive a read command from an upper layer of the front-end link and to transmit the read command in a format of the flow control digit to the physical layer of the front-end link as a first transmission flow control digit, wherein the physical layer of the front-end link is configured to transmit the first transmission flow control digit to the physical layer of the back-end link, wherein the physical layer of the back-end link is configured to transmit the first transmission flow control digit to the link layer of the back-end link as a first reception flow control digit and, and wherein the link layer of the back-end link is configured to transmit the first reception flow control digit to an upper layer of the back-end link in the format of the read command (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as credit based read/write operation is carried out between front end and back end.
As per claim 11, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 10 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the link layer of the back-end link is configured to receive a read data from the upper layer of the back-end link and to transmit the read data in the format of the flow control digit to the physical layer of the back-end link as a second transmission flow control digit, wherein the physical layer of the back-end link is configured to transmit the second transmission flow control digit to the physical layer of the front-end link, wherein the physical layer of the front-end link is configured to transmit the second transmission flow control digit to the link layer of the front-end link as a second reception flow control digit and, and wherein the link layer of the front-end link is configured to transmit the second reception flow control digit to the upper layer of the front-end link in the format of the read data (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as credit based read/write operation is carried out between front end and back end.
As per claim 12, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 11 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the link layer of the front-end link is configured to refer to a reception availability of the back-end link by referring to a credit value of the back-end link (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as credit based read/write operation is carried out between front end and back end.
As per claim 13, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 11 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the link layer of the front-end link is configured to deduct a credit value of the front-end link by the number of transmitted flow control digits, while transmitting the read command in the format of the flow control digit to the back-end link (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as credit based read/write operation is carried out between front end and back end.
As per claim 14, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 11 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the physical layer of the back-end is configured to transmit credits equal to the number of normally received flow control digits to the front-end link, when the first reception flow control digit is received from the physical layer of the front-end link (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as credit based read/write operation is carried out between front end and back end.
As per claim 15, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 11 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the link layer of the back-end link is configured to transmit the second transmission flow control digit with a credit of the back-end link (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as credit based read/write operation is carried out between front end and back end.
As per claim 16, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 15 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the link layer of the back-end link is configured to deduct a credit of the back-end link by the number of transmitted flow control digits, while transmitting the read data in the format of the flow control digit to the front-end link (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as credit based read/write operation is carried out between front end and back end.
As per claim 17, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 16 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the physical layer of the front-end link is configured to add a credit of the front-end link by number of received flow control digits, while receiving the read data in the format of the flow control digit from the back-end link (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as credit based read/write operation is carried out between front end and back end.
As per claim 18, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 11 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein when an error is included in the reception flow control digit, the link layer of the back-end link is configured to transmit a resume request to the front- end link and to stop all reception operations until the front-end link transmits a resume message (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as credit based read/write operation is carried out between front end and back end.
As per claim 19, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 18 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein when the resume request is transmitted from the back-end link, the link layer of the front-end link is configured to transmit a transmission resume message to the back-end link in response to the received resume request (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as credit based read/write operation is carried out between front end and back end.
As per claim 20, Burger, Spry, and Isenegger teach/suggest all the claimed features of claim 19 above, where Burger, Spry, and Isenegger further teach/suggest the device comprising wherein the transmission resume message is transmitted from the front-end link, the physical layer of the back-end link is configured to transmit a reception resume message to the link layer of the back-end link, and the link layer of the back-end link is configured to resume the reception operation after receiving the reception resume message from the physical layer of the back-end link (Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0046]-[0056]; [0128]-[0129]; Spry, Fig. 1; col. 2, l. 1 to col. 5, l. 31; and Isenegger, col. 1, l. 61 to col. 2, l. 49; col. 6, l. 12 to col. 10, l. 8), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as credit based read/write operation is carried out between front end and back end.
II. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 March 05, 2026