Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/4/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 8-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gertiser (US 2009/0002950 A1).
In regards to Claim 1, Gertiser discloses a printed circuit board comprising (Fig.1b, #10 is multilayer printed circuit board): a core layer (Fig.1b, #40-44); a plurality of prepreg layers (Fig.1b, #46-52); a plurality of electrically conducting layers for carrying electrical signals and/or for providing a ground plane (Fig.1b, #56/60/64), which discloses the pcb is designed to electrically connect with electronic components which provide electrical signals and ground for said components, see paragraph [0009-0011])); a first heat conducting layer (Fig.1b, #54) positioned to receive heat dissipated from one or more components (Fig.1b, #20) attached to a surface of the printed circuit board (Fig.1b, #54 conducts heat from #20), the first heat conducting layer being electrically isolated from all of the plurality of electrically conducting layers (Fig.1b and paragraph [0011-0012], which discloses #54 is isolated from the other conductive layers); a second heat conducting layer (Fig.1b, #58) positioned on an opposite side of one of the plurality of electrically conducting layers from the first heat conducting layer (Fig.1b, #58 is positioned opposite of #54), the second heat conducting layer being electrically isolated from all of the plurality of electrically conducting layers (Fig.1b and paragraph [0011-0012]); and a first plurality of heat conducting vias (Fig.1b, #68/66 (Top section of the multi-section thermal vias #68 and #66)), each of the first plurality of heat conducting vias connected between the first heat conducting layer and the second heat conducting layer (Fig.1b, #68 is connected between #54 and #58), each of the first plurality of heat conducting vias being electrically isolated from all of the plurality of electrically conducting layers (Fig.1b and paragraph [0011-0012]).
In regards to Claim 2, Gertiser discloses the printed circuit board of claim 1, wherein the first and second heat conducting layers are each electrically isolated from all of the plurality of electrically conducting layers by the core layer and/or one or more of the plurality of prepreg layers (Fig.1b, #54 are electrically isolated from all the other conductive layers via #40, and see paragraphs [0011-0012]).
In regards to Claim 3, Gertiser discloses the printed circuit board of claim 1, wherein at least some of the first plurality of heat conducting vias extend through corresponding holes defined in one or more of the plurality of electrically conducting layers (Fig.2 discloses each layer having a hole defined for the conducting vias #68).
In regards to Claim 4, Gertiser discloses the printed circuit board of claim 1, further comprising a third heat conducting layer (Fig.1b, #62) positioned on an opposite side of a second one of the plurality of electrically conducting layers from the second heat conducting layer (Fig.1b), the third heat conducting layer being electrically isolated from all of the plurality of electrically conducting layers (Paragraph [0011-0012]); and a second plurality of heat conducting vias (Fig.1b, #68 (middle section), the office interprets #68 as comprising multiple sections interconnecting one another), each of the second plurality of heat conducting vias connected between the second heat conducting layer and the third heat conducting layer (Fig.1b, #68 connects between #58 and #62), each of the second plurality of heat conducting vias being electrically isolated from all of the plurality of electrically conducting layers ((Paragraph [0011-0012]).
In regards to Claim 5, Gertiser discloses the printed circuit board of claim 4, wherein the second and third heat conducting layers are each electrically isolated from all of the plurality of electrically conducting layers by the core layer and/or one or more of the plurality of prepreg layers (Paragraph [0011-0012], which discloses all heat conductive layers 56, 58, and 62 are isolated from other conductive layers via prepreg and core layers).
In regards to Claim 6, Gertiser discloses the printed circuit board of claim 4, wherein at least some of the second plurality of heat conducting vias extend through corresponding holes defined in one or more of the plurality of electrically conducting layers (Fig.2, #68 middle section extends through holes defined by the conducting layers).
In regards to Claim 8, Gertiser discloses a method of manufacturing a printed circuit board (Fig.1b, #10), the method comprising: forming a stack comprising a core layer, a plurality of prepreg layers, and a plurality of electrically conducting layers for carrying electrical signals and/or for providing a ground plane (Fig.1, #10 includes a plurality of layers of core, prepreg and conductive layers #46-64); forming a first heat conducting layer (Fig.1b, #54) within the stack such that the first heat conducting layer receives heat dissipated from one or more components (Fig.1b, #20, the office notes heat from #20 is conducted to #54 of heat dissipation) attached to a surface of the printed circuit board and such that the first heat conducting layer is electrically isolated from all of the plurality of electrically conducting layers (paragraph [0011-0012]); forming a second heat conducting layer (Fig.1b, #58) within the stack on an opposite side of one of the plurality of electrically conducting layers from the first heat conducting layer (Fig.1b, #58 on the bottom side of #54) and such that the second heat conducting layer is electrically isolated from all of the plurality of electrically conducting layers (Paragraphs [0011-0012]); and forming a first plurality of heat conducting vias (Fig.1b, #68) connected between the first heat conducting layer and the second heat conducting layer (Fig.1b), such that each of the first plurality of heat conducting vias are electrically isolated from all of the plurality of electrically conducting layers (Paragraphs [0011-0012]).
In regards to Claim 9, Gertiser discloses the method of claim 8, wherein the first and second heat conducting layers are each electrically isolated from all of the plurality of electrically conducting layers by the core layer and/or one or more of the plurality of prepreg layers (Fig.1b each conductive layer is isolated from each other via core layer and/or prepreg, see layers #40-52 and paragraph [0009-0010]).
In regards to Claim 10, Gertiser discloses the method of claim 8, wherein at least some of the first plurality of heat conducting vias extend through corresponding holes defined in one or more of the electrically conducting layers (Fig.2, #68 extends through corresponding holes define in the one or more layers #54/58/62).
In regards to Claim 11, Gertiser discloses the method of claim 8, further comprising: forming a third heat conducting layer (Fig.1b, #62) within the stack on an opposite side of a second one of the plurality of electrically conducting layers from the second heat conducting layer (Fig.1b, #62 is opposite side of #58) and such that the third heat conducting layer is electrically isolated from all of the plurality of electrically conducting layers (Fig.1b, Paragraphs [0011-0012]); and forming a second plurality of heat conducting vias (Fig.1b, #68/66 middle section of the multi-section thermal vias) connected between the second heat conducting layer and the third heat conducting (Fig.1b, #68/66 middle section is connected between #58 and #62), such that each of the second plurality of heat conducting vias are electrically isolated from all of the plurality of electrically conducting layers (Fig.1b #68/66 are isolated from the conducting layers, see paragraph [0011-0012]).
In regards to Claim 12, Gertiser discloses the method of claim 11, wherein the first and second heat conducting layers are each electrically isolated from all of the plurality of electrically conducting layers by the core layer and/or one or more of the plurality of prepreg layers (Fig.1b each conductive layer is isolated from each other via core layer and/or prepreg, see layers #40-52 and paragraph [0009-0010]).
In regards to Claim 13, Gertiser discloses the method of claim 8, wherein at least some of the first plurality of heat conducting vias extend through corresponding holes defined in one or more of the electrically conducting layers (Fig.2, #68 extends through corresponding holes define in the one or more layers #54/58/62).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Gertiser (US 2009/0002950 A1) in view of Sharma (U.S 2019/0267319 A1).
In regards to Claim 7, Gertiser discloses the printed circuit board of claim 1.
Gertiser fails to disclose: Further comprising: a plurality of electrically conducting vias connected between corresponding ones of the plurality of electrically conducting layers; wherein at least some of the plurality of electrically conducting vias extend through corresponding holes defined in the second heat conducting layer.
However, Sharma discloses: Further comprising: a plurality of electrically conducting vias (Fig.1-2, plurality of conductive vias #112) connected between corresponding ones of the plurality of electrically conducting layers (Fig.1-2, #114 and see paragraph [0042], which discloses the conductive vias used to provide electrical and power signals to one or more components mounted on the PCB); wherein at least some of the plurality of electrically conducting vias extend through corresponding holes defined in the second heat conducting layer (Fig.2 and as such the office notes that with the combination of with Gertiser in view of Sharma, the plurality of layers provided with holes for a plurality of vias (as taught by Gertiser) would be modified to include a plurality of conductive vias (as taught by Sharma) extending through some holes to make electrical connection).
Therefore, it would of have been obvious to one of ordinary skill in the art at the time the application was filed to have modified the plurality of layers provided with holes for a plurality of vias (as taught by Gertiser) to further include a plurality of conductive vias (as taught by Sharma) extending through some holes to make electrical connection. By including conductive vias, would allow for different conductor layers to contact one or more components disposed on the printed circuit board, thereby increasing the amount of components on the circuit board.
In regards to Claim 14, Gertiser discloses the printed circuit board of claim 1.
Gertiser fails to disclose: Further comprising: a plurality of electrically conducting vias connected between corresponding ones of the plurality of electrically conducting layers; wherein at least some of the plurality of electrically conducting vias extend through corresponding holes defined in the second heat conducting layer.
However, Sharma discloses: Further comprising: a plurality of electrically conducting vias (Fig.1-2, plurality of conductive vias #112) connected between corresponding ones of the plurality of electrically conducting layers (Fig.1-2, #114 and see paragraph [0042], which discloses the conductive vias used to provide electrical and power signals to one or more components mounted on the PCB); wherein at least some of the plurality of electrically conducting vias extend through corresponding holes defined in the second heat conducting layer (Fig.2 and as such the office notes that with the combination of with Gertiser in view of Sharma, the plurality of layers provided with holes for a plurality of vias (as taught by Gertiser) would be modified to include a plurality of conductive vias (as taught by Sharma) extending through some holes to make electrical connection).
Therefore, it would of have been obvious to one of ordinary skill in the art at the time the application was filed to have modified the plurality of layers provided with holes for a plurality of vias (as taught by Gertiser) to further include a plurality of conductive vias (as taught by Sharma) extending through some holes to make electrical connection. By including conductive vias, would allow for different conductor layers to contact one or more components disposed on the printed circuit board, thereby increasing the amount of components on the circuit board.
Claims 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over QIN (CN 112492743 A) in view of Fan (U.S 2006/0180821 A1).
In regards to Claim 15, Gertiser discloses a photonic sensor comprising: a printed circuit board (PCB) having a component mounted thereto, the PCB comprising: a core layer (Fig.1b, #40-44); a plurality of prepreg layers (Fig.1b, #46-52); a plurality of electrically conducting layers for carrying electrical signals and/or for providing a ground plane (Fig.1b, #56/60/64), which discloses the pcb is designed to electrically connect with electronic components which provide electrical signals and ground for said components, see paragraph [0009-0011])); a first heat conducting layer (Fig.1b, #54) positioned to receive heat dissipated from one or more components (Fig.1b, #20) attached to a surface of the printed circuit board (Fig.1b, #54 conducts heat from #20), the first heat conducting layer being electrically isolated from all of the plurality of electrically conducting layers (Fig.1b and paragraph [0011-0012], which discloses #54 is isolated from the other conductive layers); a second heat conducting layer (Fig.1b, #58) positioned on an opposite side of one of the plurality of electrically conducting layers from the first heat conducting layer (Fig.1b, #58 is positioned opposite of #54), the second heat conducting layer being electrically isolated from all of the plurality of electrically conducting layers (Fig.1b and paragraph [0011-0012]); and a first plurality of heat conducting vias (Fig.1b, #68/66 (Top section of the multi-section thermal vias #68 and #66)), each of the first plurality of heat conducting vias connected between the first heat conducting layer and the second heat conducting layer (Fig.1b, #68 is connected between #54 and #58), each of the first plurality of heat conducting vias being electrically isolated from all of the plurality of electrically conducting layers (Fig.1b and paragraph [0011-0012]).
Gertiser fails to disclose: The component is an Light emitting diode.
However, Fan discloses: The component is an Light emitting diode (Fig.1-2, #120 and abstract, as such the office notes that with the combination of Gertiser in view of Fan, the electronic component disposed on top of the circuit board (as taught by Gertiser) would be replaced with a light emitting component (as taught by Fan) to be cooled via the thermal vias).
Therefore, it would of have been obvious to one of ordinary skill in the art at the time the application was filed to have modified the electronic component disposed on top of the circuit board (as taught by Gertiser) would be replaced with a light emitting component (as taught by Fan) to be cooled via the thermal vias. By replacing one component for another is within the purview of one ordinary skill in the art, as such modification would yield predictable results i.e., provide power to said component while also dissipate heat generated by said light emitting component.
In regards to Claim 16, Gertiser in view of Fan disclose the photonic sensor of claim 15, wherein light producing component comprises a light emitting diode or a vertical-cavity surface-emitting laser (Fan, Fig.1-2, #120 is an Light emitted diode, see abstract).
In regards to Claim 17, Gertiser in view of Fan disclose the photonic sensor of claim 15, wherein the first and second heat conducting layers are each electrically isolated from all of the plurality of electrically conducting layers by the core layer and/or one or more of the plurality of prepreg layers (Fig.1b each conductive layer is isolated from each other via core layer and/or prepreg, see layers #40-52 and paragraph [0009-0010]); and wherein at least some of the first plurality of heat conducting vias extend through corresponding holes defined in one or more of the electrically conducting layers (Fig.2, #68 extends through corresponding holes define in the one or more layers #54/58/62).
In regards to Claim 18, Gertiser in view of Fan disclose the photonic sensor of claim 15, further comprising a third heat conducting layer (Fig.1b, #62) positioned on an opposite side of a second one of the plurality of electrically conducting layers from the second heat conducting layer (Fig.1b), the third heat conducting layer being electrically isolated from all of the plurality of electrically conducting layers (Paragraph [0011-0012]); and a second plurality of heat conducting vias (Fig.1b, #68/66 (middle section), the office interprets #68/66 as comprising multiple sections interconnecting one another), each of the second plurality of heat conducting vias connected between the second heat conducting layer and the third heat conducting layer (Fig.1b, #68 connects between #58 and #62), each of the second plurality of heat conducting vias being electrically isolated from all of the plurality of electrically conducting layers ((Paragraph [0011-0012]).
In regards to Claim 19, Gertiser in view of Fan disclose the photonic sensor of claim 18, wherein the second and third heat conducting layers are each electrically isolated from all of the plurality of electrically conducting layers by the core layer and/or one or more of the plurality of prepreg layers (Paragraph [0011-0012], which discloses all heat conductive layers 56, 58, and 62 are isolated from other conductive layers via prepreg and core layers); and wherein at least some of the second plurality of heat conducting vias extend through corresponding holes defined in one or more of the plurality of electrically conducting layers (Fig.2, #68 middle section extends through holes defined by the conducting layers).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Gertiser (US 2009/0002950 A1) in view of Fan (U.S 2006/0180821 A1) and, further, in view of Wu (US 2015/0053462 A1).
In regards to Claim 20, Gertiser in view of Fan disclose the photonic sensor of claim 15.
Gertiser in view of Fan fail to explicitly disclose: Further comprising: a plurality of electrically conducting vias connected between corresponding ones of the plurality of electrically conducting layers; wherein at least some of the plurality of electrically conducting vias extend through corresponding holes defined in the second heat conducting layer.
However, Sharma discloses: Further comprising: a plurality of electrically conducting vias (Fig.1-2, plurality of conductive vias #112) connected between corresponding ones of the plurality of electrically conducting layers (Fig.1-2, #114 and see paragraph [0042], which discloses the conductive vias used to provide electrical and power signals to one or more components mounted on the PCB); wherein at least some of the plurality of electrically conducting vias extend through corresponding holes defined in the second heat conducting layer (Fig.2 and as such the office notes that with the combination of with Gertiser in view of Fan and Sharma, the plurality of layers provided with holes for a plurality of vias (as taught by Gertiser) would be modified to include a plurality of conductive vias (as taught by Sharma) extending through some holes to make electrical connection).
Therefore, it would of have been obvious to one of ordinary skill in the art at the time the application was filed to have modified the plurality of layers provided with holes for a plurality of vias (as taught by Gertiser) to further include a plurality of conductive vias (as taught by Sharma) extending through some holes to make electrical connection. By including conductive vias, would allow for different conductor layers to contact one or more components disposed on the printed circuit board, thereby increasing the amount of components on the circuit board.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Slaton (U.S 2012/0293963 A1) – Discloses a circuit board having a plurality of layers, wherein a thermal vias is disposed within said board to dissipate heat from the one or more components disposed on said circuit board.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MANDEEP S BUTTAR whose telephone number is (571)272-4768. The examiner can normally be reached 7:00AM-4:00PM.
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/MANDEEP S BUTTAR/ Primary Examiner, Art Unit 2841
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