Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated June 15, 2026, claims 1-20 are active in
this application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 12080359 [‘359]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘359
1. A method, comprising: receiving a command to read a set of memory cells; applying, in response to the command, a first read voltage to the memory cells to identify a first subset of the memory cells; and determining a programming mode of the set of memory cells.
1. A method, comprising: receiving a command to read a set of memory cells; applying, in response to the command, a first read voltage to the memory cells to identify a first subset of the memory cells; determining a programming mode of the set of memory cells; and continuing execution of the command to determine a first data item stored, via the programming mode.
2. The method of claim 1, wherein the programming mode is selected from a first mode and a second mode that store more bits per memory cell than the first mode.
2. The method of claim 1, wherein the programming mode is selected from a first mode and a second mode that store more bits per memory cell than the first mode.
3. The method of claim 2, wherein the first mode programs the set of memory cells to store one bit per memory cell; and the second mode programs the set of memory cells to store three bits per two memory cells.
3. The method of claim 2, wherein the first mode programs the set of memory cells to store one bit per memory cell; and the second mode programs the set of memory cells to store three bits per two memory cells.
4. The method of claim 2, wherein both the first mode and the second mode program threshold voltages of portions of the memory cells to a voltage region lower than the first read voltage.
4. The method of claim 2, wherein both the first mode and the second mode program threshold voltages of portions of the memory cells to a voltage region lower than the first read voltage.
5. The method of claim 2, wherein the first mode programs the memory cells to have threshold voltages within a first number of voltage regions to represent values stored in the memory cells; the second mode programs the memory cells to threshold voltages within a second number of voltage regions, more than the first number, to represent values stored in the memory cells; the first number of voltage regions include one voltage region and no more than one voltage region that is lower than the first read voltage; and the second number of voltage regions include one voltage region and no more than one voltage region lower than the first read voltage.
5. The method of claim 2, wherein the first mode programs the memory cells to have threshold voltages within a first number of voltage regions to represent values stored in the memory cells; the second mode programs the memory cells to threshold voltages within a second number of voltage regions, more than the first number, to represent values stored in the memory cells; the first number of voltage regions include one voltage region and no more than one voltage region that is lower than the first read voltage; and the second number of voltage regions include one voltage region and no more than one voltage region lower than the first read voltage.
6. The method of claim 2, wherein in response to the programming mode is the second mode, the continuing execution of the command comprises: applying a second read voltage, higher than the first read voltage to the memory cells to identify a second subset of the memory cells, wherein memory cells in the second subset are conductive under the second read voltage; determining the first data item based on identification of the first subset and the second subset.
6. The method of claim 2, wherein in response to the programming mode is the second mode, the continuing execution of the command comprises: applying a second read voltage, higher than the first read voltage to the memory cells to identify a second subset of the memory cells, wherein memory cells in the second subset are conductive under the second read voltage; determining the first data item based on identification of the first subset and the second subset.
7. The method of claim 2, wherein the first read voltage is applied to the memory cells in a first polarity; and in response to the programming mode is the second mode, the continuing execution of the command comprises: applying a second read voltage in a second polarity, opposite to the first polarity, to the memory cells to identify a second subset of the memory cells, wherein memory cells in the second subset are conductive under the second read voltage; determining the first data item based on identification of the first subset and the second subset.
7. The method of claim 2, wherein the first read voltage is applied to the memory cells in a first polarity; and in response to the programming mode is the second mode, the continuing execution of the command comprises: applying a second read voltage in a second polarity, opposite to the first polarity, to the memory cells to identify a second subset of the memory cells, wherein memory cells in the second subset are conductive under the second read voltage; determining the first data item based on identification of the first subset and the second subset.
As can be seen from the above table, similar to claim 1 of the application, the patent ‘359 recites “A method, comprising: receiving a command to read a set of memory cells; applying, in response to the command, a first read voltage to the memory cells to identify a first subset of the memory cells; and determining a programming mode of the set of memory cells.” Unlike the claim, the patent further recites “…continuing execution of the command to determine a first data item stored, via the programming mode.” As can be seen, though the claim languages are not identical, claim 1 of the patent is more limited and thus would encompass all limitations of the claim of the application. Thus, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 2-7 are rejected over claims 1-7 of patent ‘359.
Claims 8-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-13 of U.S. Patent No. 12080359 [‘359]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘359
8. A computing device, comprising: a memory device having a controller and a plurality of memory cells; and at least one processor coupled to the memory device and configured to transmit, to the memory device, a command configured to instruct the memory device to store a data item into a predetermined number of first memory cells among the plurality of memory cells; the controller of the memory device is configured to program threshold voltages of the predetermined number of first memory cells to represent the data item and the first mode.
8. A computing device, comprising: a memory device having a controller and a plurality of memory cells; and at least one processor coupled to the memory device and configured to transmit, to the memory device, a command configured to instruct the memory device to store a data item into a predetermined number of first memory cells among the plurality of memory cells; wherein in response to the command, the controller of the memory device is configured to: program, according to a first mode selected from a plurality of predefined modes, threshold voltages of the predetermined number of first memory cells to represent the data item and the first mode.
9. The computing device of claim 8, wherein the controller of the memory device is configured to program the threshold voltages of the predetermined number of first memory cells to represent the data item and the first mode, according to a first mode selected from a plurality of predefined modes.
See claim 8. “…according to a first mode selected from a plurality of predefined modes…”
10. The computing device of claim 9, wherein the threshold voltages of the predetermined number of first memory cells are programmed into a plurality of voltage regions; and the first mode is identifiable based on whether threshold voltages of one or more predetermined memory cells in the first memory cells are in a lowest voltage region among the plurality of voltage regions.
9. The computing device of claim 8, wherein the threshold voltages of the predetermined number of first memory cells are programmed into a plurality of voltage regions; and the first mode is identifiable based on whether threshold voltages of one or more predetermined memory cells in the first memory cells are in a lowest voltage region among the plurality of voltage regions.
11. The computing device of claim 9, wherein the plurality of predefined modes includes: a mode of storing one bit per memory cell; and a mode of storing more than one bit per memory cell.
10. The computing device of claim 8, wherein the plurality of predefined modes includes: a mode of storing one bit per memory cell; and a mode of storing more than one bit per memory cell.
12. The computing device of claim 11, wherein the plurality of predefined modes includes a mode of storing three bits per two memory cells.
11. The computing device of claim 10, wherein the plurality of predefined modes includes a mode of storing three bits per two memory cells.
13. The computing device of claim 12, wherein in each of the plurality of modes, the controller is configured to program a subset of the first memory cells to have threshold voltages in the lowest voltage region.
12. The computing device of claim 11, wherein in each of the plurality of modes, the controller is configured to program a subset of the first memory cells to have threshold voltages in the lowest voltage region.
14. The computing device of claim 13, wherein in each of the plurality of modes, the subset of the first memory cells is identifiable via applying a read voltage, common to the plurality of modes, to the first memory cells.
13. The computing device of claim 12, wherein in each of the plurality of modes, the subset of the first memory cells is identifiable via applying a read voltage, common to the plurality of modes, to the first memory cells.
As can be seen from the above table, similar to claim 8 of the application, the patent ‘359 recites “A computing device, comprising: a memory device having a controller and a plurality of memory cells; and at least one processor coupled to the memory device and configured to transmit, to the memory device, a command configured to instruct the memory device to store a data item into a predetermined number of first memory cells among the plurality of memory cells; the controller of the memory device is configured to program threshold voltages of the predetermined number of first memory cells to represent the data item and the first mode.” Unlike the claim, the patent further recites that the process is configured to be responsive to signals such as commands and modes. As can be seen, though the claim languages are not identical, claim 1 of the patent is more limited and thus would encompass all limitations of the claim of the application. Thus, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 9-14 are rejected over claims 8-14 of patent ‘359.
Claims 15-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14-19 of U.S. Patent No. 12080359 [‘359]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘359
15. A memory device, comprising: a plurality of memory cells; a plurality of voltage drivers connected to memory cells; and a controller coupled to the voltage drivers configured to: read first memory cells among the plurality of memory cells, increase voltages driven by the voltage drivers across the first memory cells; and determine a programming mode of the first memory cells.
14. A memory device, comprising: a plurality of memory cells; a plurality of voltage drivers connected to memory cells; and a controller coupled to the voltage drivers configured to: read first memory cells among the plurality of memory cells, increase voltages driven by the voltage drivers across the first memory cells respectively up to a first read voltage; and determine a programming mode of the first memory cells and identify further operations based on the programming mode.
16. The memory device of claim 15, wherein when a memory cell is in the conductive state, the memory cell allows larger than a predetermined threshold current to go through the memory cell; and when the memory cell is in the non-conductive state, the memory cell allows smaller than the predetermined threshold current to go through the memory cell.
15. The memory device of claim 14, wherein when a memory cell is in the conductive state, the memory cell allows larger than a predetermined threshold current to go through the memory cell; and when the memory cell is in the non-conductive state, the memory cell allows smaller than the predetermined threshold current to go through the memory cell.
17. The memory device of claim 16, wherein when the programming mode stores more than one bit per memory cell, the further operations are configured at least to further increase the voltages to a second read voltage, higher than the first read voltage, and identify a second subset of the memory cells that change from the non-conductive state to the conductive state when the voltages are driven up to the second read voltage.
16. The memory device of claim 15, wherein when the programming mode stores more than one bit per memory cell, the further operations are configured at least to further increase the voltages to a second read voltage, higher than the first read voltage, and identify a second subset of the memory cells that change from the non-conductive state to the conductive state when the voltages are driven up to the second read voltage.
18. The memory device of claim 16, wherein the first read voltage is applied in a first polarity across the first memory cells; and when the programming mode stores more than one bit per memory cell, the further operations are configured at least to reduce the voltages to zero and increase magnitudes of the voltages driven by the voltage drivers cross the first memory cells respectively up to a second read voltage in a second polarity opposite to the first polarity.
17. The memory device of claim 15, wherein the first read voltage is applied in a first polarity across the first memory cells; and when the programming mode stores more than one bit per memory cell, the further operations are configured at least to reduce the voltages to zero and increase magnitudes of the voltages driven by the voltage drivers cross the first memory cells respectively up to a second read voltage in a second polarity opposite to the first polarity.
19. The memory device of claim 16, wherein the programming mode is selected from a plurality of predefined modes, including: a mode of storing one bit per memory cell; and a mode of storing more than one bit per memory cell.
18. The memory device of claim 15, wherein the programming mode is selected from a plurality of predefined modes, including: a mode of storing one bit per memory cell; and a mode of storing more than one bit per memory cell.
20. The memory device of claim 19, wherein the plurality of predefined modes includes a mode of storing three bits per two memory cells.
19. The memory device of claim 18, wherein the plurality of predefined modes includes a mode of storing three bits per two memory cells.
As can be seen from the above table, similar to claim 15 of the application, the patent ‘359 recites “A computing device, comprising: a memory device having a controller and a plurality of memory cells; and at least one processor coupled to the memory device and configured to transmit, to the memory device, a command configured to instruct the memory device to store a data item into a predetermined number of first memory cells among the plurality of memory cells; the controller of the memory device is configured to program threshold voltages of the predetermined number of first memory cells to represent the data item and the first mode.” Unlike the claim, the patent further recites that the process is configured to be responsive to particular modes as well as the range of to increase the threshold. As can be seen, though the claim languages are not identical, claim 1 of the patent is more limited and thus would encompass all limitations of the claim of the application. Thus, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 16-20 are rejected over claims 14-19 of patent ‘359.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lasser [US Patent # 9,286,993].
With respect to claim 1, Lasser discloses a method, comprising: receiving a command to read a set of memory cells [“the controller 120 is configured to send a read command to read data from a specified address of the memory 104.” – col. 4, lines 25-30 (The patent describes a method where a controller (host) sends commands (e.g., READ) to a memory device (NAND) to access a set of cells (word line).)]; applying, in response to the command, a first read voltage to the memory cells [“the read/write circuitry 142 may be configured to apply one or more read voltages to a word line of multiple flash memory cells “ – col. 4, lines 15-20] to identify a first subset of the memory cells [“The read/write circuitry 142 may read the target group of storage elements 106 by using the first set of read voltages 170 to read storage elements having a first value of a cross-coupling flag and by using the second set of read voltages 172 to read storage elements having a second value of the cross-coupling flag…” – col. 5, lines 25-35]; and determining a programming mode [“…determination... whether... [subject] to strong or weak cross-coupling… further based on a programming process applied by the read/write circuitry 142…” – col. 5, lines 40-55 (Determining coupling strength is the direct trigger for selecting a programming mode (e.g., strong coupling requires a different mode than weak coupling). The "process applied" is the definition of the "mode" (e.g., programming algorithm/voltage).)] of the set of memory cells [“…based on a state of, or data stored in, one or more neighboring cells…" – col. 5, lines 40-55 (Defines the scope of the data affecting the determination (neighboring cells within the set).)].
With respect to claim 2, Lasser discloses the programming mode is selected from a first mode [LM-type programming plan] and a second mode [Foggy-Fine-type programming plan ] that store more bits per memory cell than the first mode. See col. 7, last paragraph; and, col. 8, lines 1-30.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by O et al. [US Patent Application # 20190354292].
With respect to claim 8, O et al. discloses a computing device [figs. 3b, 4 and 5], comprising: a memory device [111] having a controller [120] and a plurality of memory cells [“… the memory device 111a may be a … a nonvolatile memory device…” – par. 0072]; and at least one processor coupled to the memory device and configured to transmit [151/120], to the memory device, a command configured to instruct the memory device to store a data item into a predetermined number of first memory cells among the plurality of memory cells [[“… the command/address signal CMD/ADDR1 indicates a data write command, the memory device 111a may store data DAT received…” – par. 0078]; the controller of the memory device is configured to program threshold voltages of the predetermined number of first memory cells to represent the data item and the first mode [“… the command/address signal CMD/ADDR1 indicates a data write command, the memory device 111a may store data DAT received through the data pins DQP, the path selecting unit 190a and the data path 165 from the processing device 151…” – par. 0078 (, receiving a "write data" (or more accurately, a "program") command implies that the threshold voltages of a predetermined number of memory cells (a page) will be programmed.)].
With respect to claim 9, O et al. discloses the controller of the memory device is configured to program the threshold voltages of the predetermined number of first memory cells to represent the data item and the first mode, according to a first mode selected from a plurality of predefined modes [“…the processing device 151 may enter a processor mode in which one or more pre-programmed commands/address signals CMD/ADDR1 are transmitted to the corresponding memory device 111. the command/address signal CMD/ADDR1 indicates a data write command, the memory device 111a may store data DAT received through the data pins DQP, the path selecting unit 190a and the data path 165 from the processing device 151…” – pars. 0053 and 0078 (, receiving a "write data" (or more accurately, a "program") command implies that the threshold voltages of a predetermined number of memory cells (a page) will be programmed.)].
Claim(s) 15 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raghunathan et al. [US Patent # 10,043,574].
With respect to claim 15, Raghunathan et al. discloses a memory device [Abstract and claim 1], comprising: a plurality of memory cells [“plurality of memory cells”]; a plurality of voltage drivers connected to memory cells [“applying a first voltage level to control gates of a plurality of memory cells” – claim 1 (The controller commands wordline drivers to apply an initial, lower voltage to the gate of the cell to begin the process.)]; and a controller coupled to the voltage drivers configured to: read first memory cells among the plurality of memory cells, increase voltages driven by the voltage drivers across the first memory cells ["...increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level..." – Abstract ( The controller increases the voltage from the bitline driver to a higher "third" level to create a specific potential difference across the cell.)]; and determine a programming mode of the first memory cells [“The cells to be programmed to the highest target data state are programmed in one embodiment with their channels at a reference voltage (e.g., ground). The cells to be programmed to the lower target data states are programmed in one embodiment with boosted channel voltages. “ – col. 5, lines 20-30].
With respect to claim 19, Raghunathan et al. discloses the programming mode is selected from a plurality of predefined modes, including: a mode of storing one bit [“lower target data state”] per memory cell; and a mode of storing more than one bit [“highest target data state “] per memory cell [“The cells to be programmed to the highest target data state are programmed in one embodiment with their channels at a reference voltage (e.g., ground). The cells to be programmed to the lower target data states are programmed in one embodiment with boosted channel voltages. “ – col. 5, lines 20-30].
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for
all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was
made.
Claim 11 is rejected under 35 U.S.C. § 103(a) as being unpatentable over O et al. [US Patent Application # 20190354292] in view of Papandreou et al. [U.S. Patent Application # 20210149592].
O et al. discloses a computing device [figs. 3b, 4 and 5], comprising: a memory device [111] having a controller [120] and a plurality of memory cells [“… the memory device 111a may be a … a nonvolatile memory device…” – par. 0072]; and at least one processor coupled to the memory device and configured to transmit [151/120], to the memory device, a command configured to instruct the memory device to store a data item into a predetermined number of first memory cells among the plurality of memory cells [[“… the command/address signal CMD/ADDR1 indicates a data write command, the memory device 111a may store data DAT received…” – par. 0078]; the controller of the memory device is configured to program threshold voltages of the predetermined number of first memory cells to represent the data item and the first mode [“… the command/address signal CMD/ADDR1 indicates a data write command, the memory device 111a may store data DAT received through the data pins DQP, the path selecting unit 190a and the data path 165 from the processing device 151…” – par. 0078 (, receiving a "write data" (or more accurately, a "program") command implies that the threshold voltages of a predetermined number of memory cells (a page) will be programmed.)]. Additionally, O et al. discloses the controller of the memory device is configured to program the threshold voltages of the predetermined number of first memory cells to represent the data item and the first mode, according to a first mode selected from a plurality of predefined modes [“…the processing device 151 may enter a processor mode in which one or more pre-programmed commands/address signals CMD/ADDR1 are transmitted to the corresponding memory device 111. the command/address signal CMD/ADDR1 indicates a data write command, the memory device 111a may store data DAT received through the data pins DQP, the path selecting unit 190a and the data path 165 from the processing device 151…” – pars. 0053 and 0078 (, receiving a "write data" (or more accurately, a "program") command implies that the threshold voltages of a predetermined number of memory cells (a page) will be programmed.)].
O et al. discloses all of the above mentioned but is silent about the plurality of predefined modes includes: a mode of storing one bit per memory cell; and a mode of storing more than one bit per memory cell. However, this is not new. Papandreou et al. disclose that a memory array can be configured to store single, multibit or both [see claims 15 and 20]. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the O et al. memory circuit element to include the element as taught by Papandreou et al., since the modification is merely a substitution of a functionally recognized equivalent element as well as “enhance endurance of the array” [par. 0005].
Remarks
Applicant's arguments filed June 15, 2026 have been fully considered but they are not
persuasive.
Applicant argued that “Applicant’s invention as directed to adaptively selecting data programming mode and error recovery options to optimize performance, is captured by the claimed elements of the independent claims, such as claim 1 set forth below.
1. A method, comprising:
receiving a command to read a set of memory cells;
applying, in response to the command, a first read voltage to the memory cells to identify a first subset of the memory cells; and
determining a programming mode of the set of memory cells.
The prior art references Lasser (9286993), O (20190354292, and Raghunathan (10043574) fail to disclose or suggest adaptively selecting data programming mode and error recovery options to optimize performance, as claimed by Applicant.” The Examiner respectfully disagrees.
Applicant’s argument is improper because it relies on limitations not found in the actual claim language to distinguish the prior art. Applicant cannot import functional features from the specification or argument into a claim to establish patentability if those features are not explicitly recited in the claim itself.
Applicant’s argument is based on "adaptively selecting data programming mode and error recovery options to optimize performance." However, Claim 1 only broadly requires receiving a command, applying a first read voltage, and determining a programming mode. It does not contain any structural or functional limitations requiring these actions to be "adaptive," nor does it mention "error recovery options" or "optimizing performance."
The claims are given their broadest reasonable interpretation consistent with the specification. The references (Lasser, O, and Raghunathan), as demonstrated in the prior office action (which is indicated above), disclose applying a read voltage and determining a programming mode, regardless of Applicant's stated goals in the argument above. See rejections to claims 1, 2, 8, 9, 11, 15 and 19.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for response to this final action is set to expire THREE MONTHS from the date of this action. In the event a first response is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event will the statutory period for response expire later than SIX MONTHS from the date of this final action.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 July 21, 2026
Prosecution Insights