DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I (claims 1-11) in the reply filed on September 15, 2026, is acknowledged. The traversal is on the ground(s) that the groups require the same field of search and there is no undue burden on the Examiner. This is not found persuasive because a serious search and/or examination burden may be prima facie shown by appropriate explanation of separate classification, or separate status in the art, or a different field of search. In this instance, the product and process of making would require different search terms to cover the process steps of the claims and the inventions cover separate classification and have separate status in the art.
The requirement is still deemed proper and is therefore made FINAL.
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on September 15, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 17, 2025, is being considered by the examiner.
Priority
Acknowledgement is made to claim of priority to Taiwan Patent Application No. 113118367, filed May 17th, 2024
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Periyannan (US 2021/0358886 A1).
With respect to claim 1, Periyannan teaches in Figs. 9 and 15:
A semiconductor package device (semiconductor device 150), comprising:
a carrier (substrate 152);
a first chip stack (stack of semiconductor dies 114) disposed on the carrier, comprising:
a first chip (114-0) in contact with the carrier (152), wherein the first chip comprises a first through silicon via disposed on a sidewall of the first chip (edge pad 112c of die 114-0);
and a second chip (114-1) disposed on the first chip (114-0), wherein the second chip comprises a second through silicon via (112c of 114-1) disposed on a sidewall of the second chip;
and a first conductive layer extending from a surface of the first through silicon via to a surface of the second through silicon via, wherein the first conductive layer electrically connects the first chip to the second chip (ball bumps 158 and wires 156 electrically connect the edge pads of the dies).
With respect to claim 2, Periyannan further teaches:
wherein the first chip further comprising:
a substrate (dielectric film layers 128);
and bonding pads (die bond pads 116) disposed on the substrate (128).
With respect to claim 3, Periyannan further teaches:
wherein the first chip further comprising a seal ring structure embedded within the substrate.
With respect to claim 4, Periyannan further teaches:
wherein the seal ring structure (seal ring 142, labeled in Fig. 6) is laterally located between the first through silicon via (112) and the bonding pads (116).
With respect to claim 5, Periyannan further teaches:
wherein the first chip further comprising a wiring layer (metal interconnect 124) disposed between the substrate (128) and the bonding pads (116).
With respect to claim 6, Periyannan further teaches:
wherein the wiring layer extends from below the bonding pads (116) to above the first through silicon via (112).
With respect to claim 7, Periyannan further teaches:
wherein the wiring layer (124) covers the seal ring structure (142).
With respect to claim 8, Periyannan further teaches:
wherein the second chip is attached on the first chip using an adhesive layer ([0049] “The die may be affixed to each other and the substrate 152 by the DAF layer on the bottom surface of each die”)
With respect to claim 9, Periyannan further teaches:
further comprising a molding compound disposed on the carrier and laterally surrounding the first chip stack ([0059] “the device 150 may be encapsulated in a mold compound 162”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Periyannan (US 2021/0358886 A1) as applied to claim 9 above and further in view of Suh (US 2011/0227217 A1).
With respect to claim 10, Periyannan teaches all limitations of claim 9 upon which claim 10 depends. Periyannan fails to teach:
further comprising a second conductive layer disposed through the molding compound and in physical contact with the first conductive layer.
Suh teaches in Fig. 4:
further comprising a second conductive layer (filler 160 which may include a conductive paste or film [0046]) disposed through the molding compound (insulation member 140) and in physical contact with the first conductive layer (conductive patterns 130).
Periyannan discloses the claimed invention except the conductive layer being connected to a second conductive layer. Suh teaches that it is known to make an interconnect between stacked chips in which a first conductive layer is in contact with a second conductive layer. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Periyannan by Suh to include a conductive filler layer in contact with the first conductive layer for the purpose of protecting the first conductive layer and chips from external shocks and vibrations ([0046] of Suh). See MPEP 2144.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Periyannan (US 2021/0358886 A1) as applied to claim 9 above and further in view of Liao (US 10,276,543 B1).
With respect to claim 11, Periyannan teaches all limitations of claim 1 upon which claim 11 depends. Periyannan fails to teach:
further comprising a bump structure disposed on a top surface of the second chip.
Liao teaches in Fig. 8:
further comprising a bump structure (electrical terminals 160) disposed on a top surface of the second chip (upper semiconductor device 132).
Periyannan discloses the claimed invention except for the bump structure on the top surface of the second chip. Liao teaches that it is known to include a bump structure at the top of the second chip as shown in Fig. 8. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Periyannan by Liao to include bump structures at the top of the second chip, in order to form input output pads to form connections between the chips and external devices. See MPEP 2144.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
