Prosecution Insights
Last updated: October 26, 2026
Application No. 18/804,401

THERMAL ANNEALING CALIBRATION USING MICROFABRICATED RESISTANCE TEMPERATURE SENSORS

Non-Final OA §102§103
Filed
Aug 14, 2024
Examiner
SOTO, JANICE M
Art Unit
2855
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
69%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allowance Rate
239 granted / 347 resolved
+0.9% vs TC avg
Moderate +14% lift
Without
With
+13.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
22 currently pending
Career history
375
Total Applications
across all art units

Statute-Specific Performance

§101
4.5%
-35.5% vs TC avg
§103
53.8%
+13.8% vs TC avg
§102
14.9%
-25.1% vs TC avg
§112
24.1%
-15.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 347 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-8 in the reply filed on August 24, 2026 is acknowledged. Specification The disclosure is objected to because of the following informalities: The term “senor” in paragraph 00073 appears to have a typo. Perhaps applicant means “sensor”? Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Reinhard et al. (DE 102012108820) (hereinafter Reinhard). Regarding claim 1, Reinhard teaches a device, comprising: a substrate (carrier) (2); and a resistance temperature sensor (sensor) (1, 7) disposed on the substrate (carrier) (2), the resistance temperature sensor comprising a stack of alternating metal layers of a first metal (first metallic material) (4, 9) and a second metal (second metallic material) (5, 10), wherein the first metal and the second metal are different types of metals (see page 2, lines 12-26, page 6, line 25 through page 7, line 11 and Figures 1 and 3C). Regarding claim 2, Reinhard further teaches the metal layers of the first metal (first metallic material) (9) have a first thickness; the metal layers of the second metal (second metallic material) (10) have a second thickness; and the first thickness is less than the second thickness (see Figure 3C). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Reinhard in view of Lavenuta (US 6660554) (hereinafter Lavenuta). Regarding claim 3, Reinhard teaches all the limitations of claim 1. However, Reinhard does not explicitly teach the first metal comprises titanium; and the second metal comprises platinum. Lavenuta teaches a resistance temperature sensor comprising the first metal comprises titanium; and the second metal comprises platinum (column 8, lines 45-62). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify the resistance temperature sensor as taught by Reinhard with a resistance temperature sensor comprising the first metal comprises titanium; and the second metal comprises platinum as taught by Lavenuta. One would be motivated to make this combination in order to provide for the manufacture of a thermistor with leach resistant electrodes that allow for use of higher temperature solders or low fire conductive compositions to attach leads, thereby increasing the maximum operating temperature capability over that achieved in the prior art. Regarding claim 5, Reinhard teaches all the limitations of claim 1. However, Reinhard does not explicitly teach wherein the resistance temperature sensor comprises a negative temperature coefficient in which an electrical resistance of the resistance temperature sensor decreases as the resistance temperature sensor is heated at increasing temperatures. Lavenuta teaches the resistance temperature sensor comprises a negative temperature coefficient in which an electrical resistance of the resistance temperature sensor decreases as the resistance temperature sensor is heated at increasing temperatures (NTC) (see column 3, line 55). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide the resistance temperature sensor as taught by Reinhard with a negative temperature coefficient in which an electrical resistance of the resistance temperature sensor decreases as the resistance temperature sensor is heated at increasing temperature as taught by Lavenuta. One would motivated to make this combination in order to provide remote sensing, small size, or use where small temperature differences need to be measured. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Reinhard in view of Faber et al. (EP 2434267 A1) (hereinafter Faber) Regarding claim 4, Reinhard teaches all the limitations of claim 1. However, Reinhard does not explicitly teach wherein: the resistance temperature sensor comprises a resistive wire; the resistive wire comprises a first wire portion, a second wire portion, and a third wire portion disposed between the first wire portion and the second wire portion; the first wire portion and the second wire portion have a first width; the third wire portion comprises a second width, which is less than the first width. Faber teaches the resistance temperature sensor (thermal history sensor) comprises a resistive wire (thin-film line) (104) (see paragraph 0021 and Figure 1); the resistive wire comprises a first wire portion (electrodes) (1021), a second wire portion (electrodes) (1022), and a third wire portion (thin-film line) (104) disposed between the first wire portion (electrodes) (1021) and the second wire portion (electrodes) (1022); the first wire portion and the second wire portion have a first width; the third wire portion (thin-film line) (104) comprises a second width, which is less than the first width (see Figure 1 and paragraphs 0021-0022). It would have been obvious to provide the article as taught by Reinhard with the resistance temperature sensor comprises a resistive wire; the resistive wire comprises a first wire portion, a second wire portion, and a third wire portion disposed between the first wire portion and the second wire portion; the first wire portion and the second wire portion have a first width; the third wire portion comprises a second width, which is less than the first width as taught by Faber. One would be motivated to make this combination in order to provide a cost-efficient temperature sensor structure that allows temperature sensing over a wide temperature range and to facilitate integration onto semiconductor chips for thermal monitoring. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Reinhard. Regarding claim 6, Reinhard teaches all the limitations of claim 1, and further teaches the resistance temperature sensor comprising a plurality of layers (see Figures 1 and 3C). However, Reinhard does not explicitly teach the resistance temperature sensor comprises at least three metal layers of the first metal and three metal layers of the second metal. Although Reinhard does not explicitly teach the resistance temperature sensor comprises at least three metal layers of the first metal and three metal layers of the second metal, it would have been obvious to one having ordinary skill in the art at the time the invention was made to provide the resistance temperature sensor comprising at least three metal layers of the first metal and three metal layers of the second metal, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. S1. Regis Paper Co. v. Bemis Co., 193 USPQ8. One would be motivated to make this combination in order to improve sensitivity and resolution of the temperature sensor. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Reinhard in view of Harrabi (US 2020/0240847) (hereinafter Harrabi). Regarding claim 7, Reinhard teaches all the limitations of claim 1. However, Reinhard does not explicitly teach the resistance temperature sensor is a component of a test structure that is disposed on the substrate; the test structure emulates a geometric structure of a quantum device comprising a Josephson junction; and the resistance temperature sensor emulates a size and placement of the Josephson junction of the quantum device. Harrabi teaches the resistance temperature sensor (temperature sensor) (5) is a component of a test structure that is disposed on the substrate (substrate) (2) (see Figure 2 and paragraph 0029); the test structure (superconductive layer) (3) emulates a geometric structure of a quantum device comprising a Josephson junction (see Figures 1A-1B and 2); and the resistance temperature sensor (temperature sensor) (5) emulates a size and placement of the Josephson junction of the quantum device (see Figure 2 and paragraphs 0002 and 0009). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide the device as taught by Reinhard with the resistance temperature sensor is a component of a test structure that is disposed on the substrate; the test structure emulates a geometric structure of a quantum device comprising a Josephson junction; and the resistance temperature sensor emulates a size and placement of the Josephson junction of the quantum device as taught by Harrabi. One would be motivated to make this combination in order to efficiently control and monitor the temperature of the Josephson junction and to monitor hotspots. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Reinhard in view of Harrabi as applied to claim 7 above, in further view of Chow et al. (US 2020/0403138) (hereinafter Chow). Regarding claim 8, Reinhard as modified by Harrabi teaches all the limitations of claim 7. However, Reinhard as modified by Harrabi does not explicitly teach the quantum device comprises a superconducting quantum bit. Chow teaches the quantum device comprises a superconducting quantum bit (see paragraph 0008). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide the quantum device as taught by the prior combination with a superconducting quantum bit as taught by Chow. Qubits operate as more sophisticated processors of information, enabling quantum computers to function in ways that allow them to solve difficult problems that are intractable using conventional computers. A superconducting qubit includes a Josephson junction (Josephson junction). A Josephson junction is a superconducting tunnel junction, which is formed by separating two thin-film superconducting metal layers by a non-superconducting material. When the metal in the superconducting layers is caused to become superconducting—e.g. by reducing the temperature of the metal to a specified cryogenic temperature—pairs of electrons can tunnel from one superconducting layer through the non-superconducting layer to the other superconducting layer. One would be motivated to make this combination in order to monitor and control the reduction of the temperature of the metal to a specified cryogenic temperature to allow pairs of electrons can tunnel from one superconducting layer through the non-superconducting layer to the other superconducting layer as known in the art. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. JPS63280471 A directed to a temperature control method of a Josephson element. Notarys et al. (US 3911333) directed to a multilayer thin film superconductive device and method of making the same, the superconductive device forming a Josephson junction. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M SOTO whose telephone number is (571)270-7707. The examiner can normally be reached M-F 8:00am-4:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Breene can be reached at 571-272-4107. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JANICE M SOTO/Examiner, Art Unit 2855 /JOHN E BREENE/Supervisory Patent Examiner, Art Unit 2855
Read full office action

Prosecution Timeline

Aug 14, 2024
Application Filed
Sep 30, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
69%
Grant Probability
83%
With Interview (+13.9%)
3y 2m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 347 resolved cases by this examiner. Grant probability derived from career allowance rate.

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