Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 2-21 were previously examined.
Claim 7 is amended on February 6, 2026.
Claims 2-21 are pending on this examination.
Response to Arguments
Applicant's arguments, see under “Objections to Drawings” filed February, 6, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments:
On page 7 of the remark, Applicant wrote that FIG. 3, are appropriate because more-detailed illustration is not essential for a proper understanding of the features of claims 2, 10, and 16. In this case, a person having ordinary skill in the art would understand, from the Specification and the Drawings, how the ''first circuitry" may "receive a first signal ... comprising a first bit ... indicating whether a memory system detected a first error associated with first data received by the memory system," and "a second signal ... comprising a second bit ... indicating whether a host system detected a second error associated with the first data," as recited in claim 2…. person having ordinary skill in the art would understand from the Specification and Drawings that the recited "first circuitry" that "receive[s] a first signal ... comprising a first bit ... indicating whether a memory system detected a first error associated with first data received by the memory system," and "a second signal ... comprising a second bit ... indicating whether a host system detected a second error associated with the first data," as recited in independent claim 2, is referring to the "syndrome check circuit 335"
In responses:
Examiner disagreed because Figure 3 does not clearly indicate or label which of the elements below is considered a first circuitry or a second circuitry.
Examiner disagreed because Paragraph [0124] is the only paragraph in the specification discloses “first circuitry” and “second circuitry”. No other paragraphs mention about first circuitry and second circuitry.
Examiner disagreed because [0124] does not have element number such as 305, 310, 315, 320, 335, 360, 370, 375 and extra for “first circuitry” and “second circuitry”.
Therefore, Examiner disagreed because an ordinary person would not know which of the circuitries on figure 3 above is considered a first circuitry and/or a second circuitry at all. The ordinary person cannot assume that (1) memory system 310, (2) host system 305, (3) syndrome check circuit 335, (4) error control circuit 315, (5) first set of log gates 360, (6) second set of logic gates 365, (7) 370, (8) 375 and other circuitries on figure 3 as a first circuitry and/or a second circuitry at all. In addition, Applicant fails to clearly point out which of the that (1) memory system 310, (2) host system 305, (3) syndrome check circuit 335, (4) error control circuit 315, (5) first set of log gates 360, (6) second set of logic gates 365, (7) 370, (8) 375 and other circuitries on figure 3 is or are considered as a first circuitry and/or a second circuitry.
In responses:
Examiner disagrees because figure 3 (see below) shows a memory system 310 with I/O signals 380 and 325. However, Fig. 3 do not show any circuitry within memory system 310 that can detect a first error associated within memory system 310. Therefore, An ordinary person would not know how to setup circuitries so that memory system detected a first error associated with first data received by the memory system. As such, it is unclear how “a memory system detected a first error associated with first data received by the memory system” as claimed
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As such, the drawing objection is maintained.
Applicant's arguments, see under “35 USC 101” filed February, 6, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments:
On page 12 of the remark, Applicant argued that claim 2 cannot practically be performed in the human mind. For example, the human mind is not equipped to "receive a first signal having a first signal level and comprising a first bit, and a second signal having a second signal level and comprising a second bit," or "perform an error control operation on the first data," as recited in independent claim 2. . Therefore, for at least these reasons, independent claim 2 does not recite a mental process, nor does independent claim 2 recite any other abstract idea, law of nature, or natural phenomenon.
In responses:
Examiner disagrees because the mental processes can receive a first signal (such as first data) and a second signal (such as second data) wherein the first data comprising a first level and first bit and wherein the second data comprising a second level and a second bit.
Examiner disagrees because the mental compare the first level against a second level. The mental compare the first bit against a second bit.
Examiner disagrees because the recited claim 2 does not utilize the comparison result for improving the functioning of a system after performing comparison at all.
As such, the mental process can perform comparison between first signal and second signal based on mathematical process.
Applicant’s arguments:
On pages 13-14 of the remark, Applicant argued that claims should not reject under 101 abstract rejection because the recited claim improves the functioning of a system that includes the memory device.
Applicant provides different examples from specification.
In some cases, the error control circuit 315 may generate an output indicating whether the error control circuit 315 detected an error in the data, or whether the error control circuit 315 detected and attempted to correct an error in the data, or both. For example, if the error control circuit 315 is included in the memory system 310, the output of the error control circuit 315 may be a first value (e.g., a high voltage, a logical "l'J if the error control circuit 315 detected an error in the data or attempted to correct an error in that data. Alternatively, the output of the error control circuit 315 may be a second value (e.g., a low voltage or logical "O'J if the error control circuit 315 did not detect an error in the data (e.g., if the data did not contain an error or if the data contained an undetectable error, such as an MBE is the error control circuit does not include the DED component 320).
Specification ,i [0050] (emphasis added). The Specification explains that the characteristics of the signals may be used to determine types of errors of the data, stating:
For example, during an access operation for data stored in the memory system, the syndrome check circuitry may receive a first signal from the memory system indicating whether the memory system detected and attempted to correct an error in the data and a second signal from the host system indicating whether the host system detected an error in the received data. The syndrome check circuitry may determine characteristics of (e.g., compare) the first signal and the second signal using the additional circuitry to differentiate between different combinations of errors detected at the memory system and the host system. For example, the additional circuitry may be configured to determine whether the memory system detected an error and the host system did not detect an error, whether the memory system did not detect an error and the host system detected an error, whether both the memory system and the host system detected an error, or whether neither the memory system nor the host system detected an error, or various combinations thereof. Accordingly, the syndrome check circuitry may support improved diagnostic capabilities, for example by allowing four distinct error states to be detected, rather than a syndrome check circuit configured to detect either the host system or the memory system detected an error, or whether neither the memory system nor the host system detected an error (e.g., two error states). In some case[s], the host system, the memory system, or both may use the improved diagnostic information to further improve reliability of data communicated between the host system and the memory system, among other advantages. See id ,i [0013] (emphasis added).
In Responses:
Examiner disagrees because the recited claim 2 does not utilize the comparison result for improving the functioning of a system after performing comparison at all.
Examiner disagrees because comparison between first signal and second signal clearly does not improve any functionally of any system at all.
As such, the rejection is maintained.
Applicant's arguments, see under “35 USC 112b” filed February, 6, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments:
Applicant’s arguments for 35 USC 112b are similar to arguments above (see drawing objection arguments above).
In Responses:
As such, see Examiner response above.
Applicant's arguments, see under “35 USC 102” filed February, 6, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments:
Applicant wrote that Bains merely discusses the comparison of two sets of ECC bits to detect an error, and is silent as to receiving a signal indicating "whether a memory system detected a first error associated with first data," let alone also receiving a signal indicating "whether a host system detected a second error associated with the first data," as recited in independent claim 2. Thus, Bains does not disclose all features recited in independent claim 2.
In Responses:
Examiner disagrees because Fig. 3 does not show any circuitry within Memory System 310 detects a first error associated with first data. 380 and 325 are output signals.
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Therefore, Examiner disagrees because the local generated ECC from ECC computation 508 can indicate whether the first data (DATA_64) detected an error associated with first data (DATA_64). It is well-known that ECC data can indicate that the data an error associated with data. Examiner disagrees because the host generated ECC can indicate whether the detected an error associated with first data (DATA_64). It is well-known that ECC data can indicate that the data an error associated with data.
As such, the rejection is maintained.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Claim 2 recites “first circuitry” and “second circuitry”
Paragraph [0124] is the only paragraph in the specification discloses “first circuitry” and “second circuitry”. No other paragraphs mention about first circuitry and second circuitry.
(Applicant [0124] An apparatus, including: first circuitry … second circuitry)
However, figures 1-8 do not clearly show or label “first circuitry” and “second circuitry”. As such, it is unclear where the 1st/2nd circuitry is.
Therefore, the “first circuitry” and “second circuitry” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claims 2, 10 and 16 recite a limitation such as “whether a memory system detected a first error associated with first data received by the memory system”
Fig. 3 shows a memory system 310 with I/O signals 380 and 325.
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However, Fig. 3 do not show any circuitry within memory system 310 that can detect a first error associated within memory system 310. As such, it is unclear how “a memory system detected a first error associated with first data received by the memory system” as claimed.
Therefore, the “memory system detected a first error associated with first data received by the memory system” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 7 recites “the second circuitry further comprising: a plurality of logic gates; …”
Figure 3 shows “a plurality of logic gates”. However, figure 3 does not show a second circuitry further comprising: a plurality of logic gates.
Which element in figure 3 is considered a second circuitry? 335?
Therefore, the “the second circuitry further comprising: a plurality of logic gates” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 2-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
In analyzing under step 1, is the claim to a process, machine manufacture or composition of matter? Yes.
In analyzing under step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes.
The claim(s) 2, 10 and 16 recite(s) the abstract limitations such as “… receive a first signal having a first signal level and comprising a first bit, and a second signal having a second signal level and comprising a second bit (receiving input data for comparing)… operable to perform an error control operation on the first data based at least in part on comparing the value of the first bit with the value of the second bit and based at least in part on comparing a level of the first signal to a level of the second signal” (comparing two input data)… is a process that, under its broadest reasonable interpretation, covers performance of the limitation under mathematical processes but for the recitation of generic computer processor such as “a first circuitry and a second circuitry” (see claim 2), “second circuitry further comprising: a plurality of logic gates; and a plurality of inverters” (see claim 7) “a non-transitory memory and a processor “ (see claim 16)
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components and software module, then it falls within the “Mathematical Processes” grouping of abstract ideas.
Accordingly, the claim recites an abstract limitation.
This judicial exception is not integrated into a practical application under Step 2A Prong 2. The recited steps of " receive a first signal having a first signal level and comprising a first bit, and a second signal having a second signal level and comprising a second bit" are extra-solution activity to the judicial exception, and hence these features are not indicative of integration into a practical application.
In analyzing under step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO.
This judicial exception is not integrated into a practical application because the claims recite a generic processor such as “a first circuitry and a second circuitry” (see claim 2) “a non-transitory memory and a processor “ (see claim 16) for comparing.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because a generic processor and software module which are high level of generality performing comparation.
Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
In analyzing under step 2B, does the claim recite additional elements that amount to significantly more than the judicial exception? NO
Claims 2-21 do not recite any additional elements except a generic processor such as for comparing. Accordingly, the additional generic elements do not amount to significantly more than the judicial exception because a generic processor and software module which are high level of generality performing comparison
The claim is directed to an abstract idea.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites a limitation such as “first circuitry operable to receive a first signal … and a second signal …second circuitry coupled with the first circuitry … comparing the value of the first bit with the value of the second bit and based at least in part on comparing a level of the first signal to a level of the second signal”
The recited limitation such as “first circuitry operable to receive a first signal … and a second signal.. second circuitry… comparing a level of the first signal to a level of the second signal” renders this limitation indefinite because Applicant fails to provide what first circuitry can receive both 1st and 2nd signals and what second circuitry can compare 1st and 2nd signals. It is unclear what circuitry can receive and/or compare 1st and 2nd signals.
Claims 2, 10 and 16 recite a limitation such as “whether a memory system detected a first error associated with first data received by the memory system”
The recited limitation such as “a memory system detected a first error associated with first data received by the memory system” render this limitation indefinite because 1st and/or 2nd circuitry do not connect to a memory system. As such, it is unclear how 1st and/or 2nd circuitry can receive a first/second error from memory system or the host system. The memory system is not part of the apparatus as claimed.
Claims 2, 10 and 16 recite a limitation such as “whether a host system detected a second error associated with the first data”
The recited limitation such as “whether a host system detected a second error associated with the first data” ” render this limitation indefinite because 1st and/or 2nd circuitry do not connect to a host system. As such, it is unclear how 1st and/or 2nd circuitry can receive a first/second error from memory system or the host system. The host system is not part of the apparatus as claimed. Applicant does not provide a method of (memory system 310 or host system 305) performing any detection at all.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-6, 8-21 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Bains et al (US 2009/0,249,169)
As per claim 1: (canceled)
As per claim 2:
Bains discloses:
An apparatus, comprising:
(Bains, Fig. 1 Memory Controller 110 (host), Memory Device 130)
(Bains, Fig. 5, ECC 505, ECC Computation 508, Comparator 512, Error Correction 506)
(Bains, Fig. 6 comparing the locally generated error check bit with the host generated error check bits 610)
(Bains, [0016] Computing system 100 includes requester 102, memory controller (or host) 110, memory device 130, and interconnect 120)
(Bains, [0035] Comparator 512 compares the computed ECC bits (e.g., locally generated ECC bits) with the stored ECC bits (e.g., host generated ECC bits such as ECC bits 505). If the two sets of ECC bits match, then comparator 512 asserts a MATCH signal. If the computed ECC bits do not match the stored ECC bits, then data bits 503 may contain an error.. DRAM 500 includes ECC correction logic 506 to correct certain errors)
first circuitry operable to receive a first signal having a first signal level and comprising a first bit, and a second signal having a second signal level and comprising a second bit,
(Bains, Fig. 5, ECC 505, ECC Computation 508, Comparator 512, Error Correction 506)
(Bains, Fig. 5 Comparator 512 to receive first signal and second signal from 508 and 523)
(Bains, [0035] Comparator 512 compares the computed ECC bits (e.g., locally generated ECC bits) with the stored ECC bits (e.g., host generated ECC bits such as ECC bits 505). If the two sets of ECC bits match, then comparator 512 asserts a MATCH signal. If the computed ECC bits do not match the stored ECC bits, then data bits 503 may contain an error)
a value of the first bit indicates whether a memory system detected a first error associated with first data received by the memory system and
(Bains, Fig. 5, ECC computation 508 to generate ECC 8 bits)
(Bains, [0035] Comparator 512 compares the computed ECC bits (e.g., locally generated ECC bits) with the stored ECC bits (e.g., host generated ECC bits such as ECC bits 505). If the two sets of ECC bits match, then comparator 512 asserts a MATCH signal. If the computed ECC bits do not match the stored ECC bits, then data bits 503 may contain an error)
a value of the second bit indicates whether a host system detected a second error associated with the first data; and
(Bains, Fig. 5, ECC 505, Mux 523, Output to Comparator 512)
(Bains, [0035] Comparator 512 compares the computed ECC bits (e.g., locally generated ECC bits) with the stored ECC bits (e.g., host generated ECC bits such as ECC bits 505). If the two sets of ECC bits match, then comparator 512 asserts a MATCH signal. If the computed ECC bits do not match the stored ECC bits, then data bits 503 may contain an error)
second circuitry coupled with the first circuitry and operable to perform an error control operation on the first data
(Bains, Fig. 5, Corrected Data 514, Optional Error Log Uncorrectable Error 5120 which coupled to Comparator 512)
based at least in part on comparing the value of the first bit with the value of the second bit and based at least in part on comparing a level of the first signal to a level of the second signal.
(Bains, [0035] Comparator 512 compares the computed ECC bits (e.g., locally generated ECC bits) with the stored ECC bits (e.g., host generated ECC bits such as ECC bits 505). If the two sets of ECC bits match, then comparator 512 asserts a MATCH signal. If the computed ECC bits do not match the stored ECC bits, then data bits 503 may contain an error.. DRAM 500 includes ECC correction logic 506 to correct certain errors)
(Bains, Fig. 5, Comparator 512 to output Match or SBC)
As per claim 3:
Bains further discloses:
wherein the second circuitry is further operable to: output a third signal indicating a type of error
(Bains, Fig. 5, Comparator 512 to output Match or SBC)
associated with the first data based at least in part on comparing the value of the first bit to the value of the second bit, and based at least in part on comparing an inverse of the level of the first signal to the level of the second signal, the level of the first signal to an inverse of the level of the second signal, and the inverse of the level of the first signal to the inverse of the level of the second signal.
(Bains, Fig. 5, ECC 505, ECC Computation 508, Comparator 512, Error Correction 506)
(Bains, [0035] Comparator 512 compares the computed ECC bits (e.g., locally generated ECC bits) with the stored ECC bits (e.g., host generated ECC bits such as ECC bits 505). If the two sets of ECC bits match, then comparator 512 asserts a MATCH signal. If the computed ECC bits do not match the stored ECC bits, then data bits 503 may contain an error.. DRAM 500 includes ECC correction logic 506 to correct certain errors)
As per claim 4:
Bains further discloses:
wherein the third signal indicates that the memory system did not detect an error in the first data
(Bains, Fig. 5, Comparator 512 to output Match or SBC)
based at least in part on the first signal level comprising a first magnitude and that the host system did not detect an error in the first data based at least in part on the second signal level comprising a second magnitude different than the first magnitude.
(Bains, [0035] Comparator 512 compares the computed ECC bits (e.g., locally generated ECC bits) with the stored ECC bits (e.g., host generated ECC bits such as ECC bits 505). If the two sets of ECC bits match, then comparator 512 asserts a MATCH signal. If the computed ECC bits do not match the stored ECC bits, then data bits 503 may contain an error.. DRAM 500 includes ECC correction logic 506 to correct certain errors)
As per claim 5:
Bains further discloses:
wherein outputting the third signal further comprises: inverting the first signal, the second signal, or both, to indicate a type of the error.
(Bains, Fig. 5, Comparator 512 to output Match or SBC)
As per claim 6:
Bains further discloses:
wherein the second circuitry is further operable to:
detect a single-bit error at the memory system, a multi-bit error at the memory system, a single-bit error at the host system, or a multi-bit error at the host system, or any combination thereof based at least in part on comparing the value of the first bit with the value of the second bit and based at least in part on comparing a level of the first signal to a level of the second signal,
(Bains, [0035] Comparator 512 compares the computed ECC bits (e.g., locally generated ECC bits) with the stored ECC bits (e.g., host generated ECC bits such as ECC bits 505). If the two sets of ECC bits match, then comparator 512 asserts a MATCH signal. If the computed ECC bits do not match the stored ECC bits, then data bits 503 may contain an error.. DRAM 500 includes ECC correction logic 506 to correct certain errors)
wherein performing the error control operation is based at least in part on the detecting.
(Bains, [0035] … If the computed ECC bits do not match the stored ECC bits, then data bits 503 may contain an error.. DRAM 500 includes ECC correction logic 506 to correct certain errors)
As per claim 8:
Bains further discloses:
a register operable to store second data representative of one or more outputs from the second circuitry.
(Bains, Fig. 5, ECC 505, ECC Computation 508, Comparator 512, Error Correction 506)
(Bains, [0043] … "hardware" include, but are not limited to, an integrated circuit, a finite state machine, or even combinatorial logic. The integrated circuit may take the form of a processor such as a microprocessor, an application specific integrated circuit, a digital signal processor, a micro-controller, or the like)
As per claim 9:
Bains further discloses:
wherein the first signal is received from the memory system and
((Bains, [0039] ECC computation logic (e.g., ECC computation logic 508, shown in FIG. 5) computes locally generated error check bits.)
(Bains, [0035] Comparator 512 compares the computed ECC bits (e.g., locally generated ECC bits) with the stored ECC bits (e.g., host generated ECC bits such as ECC bits 505). If the two sets of ECC bits match, then comparator 512 asserts a MATCH signal. If the computed ECC bits do not match the stored ECC bits, then data bits 503 may contain an error)
the second signal is received from the host system.
(Bains, [0035] Comparator 512 compares the computed ECC bits (e.g., locally generated ECC bits) with the stored ECC bits (e.g., host generated ECC bits such as ECC bits 505). If the two sets of ECC bits match, then comparator 512 asserts a MATCH signal. If the computed ECC bits do not match the stored ECC bits, then data bits 503 may contain an error)
(Bains, [0040] Referring to process block 608, the host generated error check bits are read (e.g., from bank 504, shown in FIG. 5)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bains et al (US 2009/0,249,169), in view of Derner et al. (US 6,834,022)
As per claim 7:
Bains further discloses the second circuitry comprising variation of combinatorial logic and other circuit alike… are operable to perform the error control operation on the first data.
(Bains, Fig. 5, ECC 505, ECC Computation 508, Comparator 512, Error Correction 506)
(Bains, [0043] … "hardware" include, but are not limited to, an integrated circuit, a finite state machine, or even combinatorial logic. The integrated circuit may take the form of a processor such as a microprocessor, an application specific integrated circuit, a digital signal processor, a micro-controller, or the like)
However Bains does not clearly disclose the second circuitry further comprising: a plurality of logic gates; and a plurality of inverters, wherein the plurality of logic gates and the plurality of inverters
Derner discloses the second circuitry further comprising: a plurality of logic gates; and a plurality of inverters, wherein the plurality of logic gates and the plurality of inverters
(Derner, Column 9 and Fig. 6 shows each of the compare units 518-0 to 518-3 includes a plurality of logic gates and inverters indicated by AND gates 651 and 652 and inverters 653. AND gates 651 and inverters 653 connect to inputs A and B to operate as a decoder to decode different combination of the signals provided on lines 512(N-1) and 512-N)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate a combination logic of Derner in order to design circuitry with a plurality of logic gates and a plurality of inverters.
(Derner, Column 9 and Fig. 6 shows each of the compare units 518-0 to 518-3 includes a plurality of logic gates and inverters indicated by AND gates 651 and 652 and inverters 653. AND gates 651 and inverters 653 connect to inputs A and B to operate as a decoder to decode different combination of the signals provided on lines 512(N-1) and 512-N)
As per claims 10-15:
Method of claims 10-15 recite similar limitations as claims 1-9. As such, see rejection above.
As per claims 16-21:
Method of claims 16-21 recite similar limitations as claims 1-9. As such, see rejection above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THIEN DANG NGUYEN whose telephone number is (571)272-9189. The examiner can normally be reached Monday-Friday 7 AM - 3:30 PM.
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/Thien Nguyen/Primary Examiner, Art Unit 2111