Prosecution Insights
Last updated: April 19, 2026
Application No. 18/804,592

LASER DICING GLASS WAFERS USING ADVANCED LASER SOURCES

Non-Final OA §102§103§DP
Filed
Aug 14, 2024
Examiner
TENTONI, LEO B
Art Unit
1742
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Applied Materials, Inc.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 11m
To Grant
92%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
1134 granted / 1386 resolved
+16.8% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
27 currently pending
Career history
1413
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
48.3%
+8.3% vs TC avg
§102
20.7%
-19.3% vs TC avg
§112
19.0%
-21.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1386 resolved cases

Office Action

§102 §103 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The disclosure is objected to because of the following informalities: On page 1, the status of the parent application should be updated (the information should include the application number, the filing date and the patent number). Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Ono et al (U.S. Patent Application Publication 2020/0058550 A1). Regarding claim 1, Ono et al (see the entire document, in particular, paragraphs [0002], [0018], [0025] and [0038]; Figures 1, 5 and 10) teaches a process (see paragraph [0002] (method of manufacturing a semiconductor device (semiconductors include semiconductor waveguides for optical applications)) of Ono et al), including (a) forming a plurality of voids within a substrate along a dicing path by exposing the substrate to a first burst of laser pulses at a first location along the dicing path of a respective waveguide combiner, the substrate having a plurality of waveguides, each laser pulse within the first burst forming a respective void within a first column at the first location to form a plurality of voids (see Figure 1, paragraph [0018] (semiconductor wafer W, chip regions Rchip, dicing regions Rd), Figure 10, paragraph [0038] (modified parts LM (i.e., voids) in modified layer 31), Figure 5, paragraph [0025] (laser oscillator 120 operates laser light 121 in the form of pulses) of Ono et al); and (b) exposing the substrate to a second burst of laser pulses at a second location along the dicing path of the respective waveguide combiner, each laser pulse within the second burst forming the respective void within a second column at the second location to form the plurality of voids, the first column and the second column are spaced by a pitch between a center of the first column and the second column along the dicing path (see Figure 1, paragraph [0018] (semiconductor wafer W, chip regions Rchip, dicing regions Rd), Figure 10, paragraph [0038] (modified parts LM (i.e., voids) in modified layer 32; modified layers 31 and 32 are arranged in a plurality of rows at different positions in the thickness direction (z-direction)), Figure 5, paragraph [0025] (laser oscillator 120 operates laser light 121 in the form of pulses) of Ono et al). Claim(s) 8 and 15 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Ono et al (U.S. Patent Application Publication 2020/0058550 A1). Regarding claim 8, Ono et al (see the entire document, in particular, paragraphs [0002], [0018], [0025] and [0038]; Figures 1, 5 and 10) teaches a process (see paragraph [0002] (method of manufacturing a semiconductor device (semiconductors include semiconductor waveguides for optical applications)) of Ono et al), including (a) exposing a substrate to a first plurality of laser pulses at a first location along a dicing path of a respective waveguide combiner, the substrate having a plurality of waveguides, each laser pulse within the first plurality of laser pulses forming a respective void within a first column at the first location to form a plurality of voids (see Figure 1, paragraph [0018] (semiconductor wafer W, chip regions Rchip, dicing regions Rd), Figure 10, paragraph [0038] (modified parts LM (i.e., voids) in modified layer 31), Figure 5, paragraph [0025] (laser oscillator 120 operates laser light 121 in the form of pulses) of Ono et al); and (b) exposing the substrate to a second plurality of laser pulses at a second location along the dicing path of the respective waveguide combiner, each laser pulse within the second plurality of laser pulses forming the respective void within a second column at the second location to form a plurality of voids, the first column and the second column are spaced by a pitch between a center of the first column and the second column along the dicing path (see Figure 1, paragraph [0018] (semiconductor wafer W, chip regions Rchip, dicing regions Rd), Figure 10, paragraph [0038] (modified parts LM (i.e., voids) in modified layer 32; modified layers 31 and 32 are arranged in a plurality of rows at different positions in the thickness direction (z-direction)), Figure 5, paragraph [0025] (laser oscillator 120 operates laser light 121 in the form of pulses) of Ono et al). Regarding claim 15, see Figure 10. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 2, 3, 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al (U.S. Patent Application Publication 2020/0058550 A1) as applied to claim 1 above, and further in view of Sun (U.S. Patent Application Publication 2019/0299329 A1). Regarding claim 2, Ono et al does not teach (1) laser pulses having a wavelength of about 1.0 µm to about 5 µm. Sun (see the entire document, in particular, paragraphs [0001], [0032], [0035], [0036], [0041] and [0068]) teaches a process (see paragraph [0001] (laser micromachining methods) of Sun), including laser pulses having a wavelength of about 1.0 µm to about 5 µm (see paragraph [0036] (laser pulse wavelength of 0.2 - 2µm) of Sun), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide laser pulses having a wavelength of about 1.0 µm to about 5 µm in the process of Ono et al in view of Sun in order to process layers of a device without damaging the substrate (see paragraph [0068] of Sun). Regarding claim 3, see paragraph [0041] (target may be glass (i.e., silicon dioxide); bandgap of silicon dioxide is about 9 eV) of Sun. Regarding claim 6, see paragraph [0035] (burst 110 may include any number of laser pulses; 3 – 10 laser pulses) of Sun. Regarding claim 7, see paragraph [0036] (pulse repetition frequency of 100 kHz – 300 MHz) of Sun. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al (U.S. Patent Application Publication 2020/0058550 A1) as applied to claim 1 above, and further in view of Xu et al (U.S. Patent Application Publication 2011/0240617 A1). Regarding claim 4, Ono et al does not teach (1) a laser pulse having a pulse energy of less than about 100 µJ. Xu et al (see the entire document, in particular, paragraphs [0005], [0013], [0026] and [0134]) teaches a process (see paragraph [0005] (machining materials using pulsed lasers) of Xu et al), including a laser pulse having a pulse energy of less than about 100 µJ (see paragraph [0026] (pulse energy of 0.1 - 500µJ) of Xu et al), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a laser pulse having a pulse energy of less than about 100 µJ in the process of Ono et al in view of Xu et al in order to efficiently machine materials while avoiding mechanically or thermally weakening the material (see paragraph [0013] of Xu et al). Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al (U.S. Patent Application Publication 2020/0058550 A1) as applied to claim 1 above, and further in view of Marjanovic et al (U.S. Patent Application Publication 2015/0166396 A1). Regarding claim 5, Ono et al does not teach (1) voids having a diameter of less than about 2 µm. Marjanovic et al (see the entire document, in particular, paragraphs [0003], [0005], [0006] and [0012]) teaches a process (see paragraph [0006] (methods of forming holes in glass using a pulsed laser) of Marjanovic et al), including voids having a diameter of less than about 2 µm (see paragraph [0012] (glass article having a hole diameter of 1 – 100 microns) of Marjanovic et al), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide voids having a diameter of less than about 2 µm in the process of Ono et al in view of Marjanovic et al in order to form holes of sufficient quality at a high enough rate (see paragraph [0005] of Marjanovic et al). Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al (U.S. Patent Application Publication 2020/0058550 A1) as applied to claims 8 and 15 above, and further in view of Sun (U.S. Patent Application Publication 2019/0299329 A1). Regarding claim 9, Ono et al does not teach (1) a laser pulse width of less than about 12 picoseconds. Sun (see the entire document, in particular, paragraphs [0001], [0032], [0035], [0036], [0041] and [0068]) teaches a process (see paragraph [0001] (laser micromachining methods) of Sun), including a laser pulse width of less than about 12 picoseconds (see paragraph [0032] (pulse width of less than 10 picoseconds) of Sun), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a laser pulse width of less than about 12 picoseconds in the process of Ono et al in view of Sun in order to process layers of a device without damaging the substrate (see paragraph [0068] of Sun). Regarding claim 10, see paragraph [0036] (pulse repetition frequency of 100 kHz – 300 MHz) of Sun. Regarding claim 11, see paragraph [0035] (burst 110 may include any number of laser pulses; 3 – 10 laser pulses) of Sun. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al (U.S. Patent Application Publication 2020/0058550 A1) in combination with Sun (U.S. Patent Application Publication 2019/0299329 A1) as applied to claims 8-11 and 15 above, and further in view of Vanagas et al (U.S. Patent Application Publication 2017/0250113 A1). Regarding claim 12, Ono et al (in combination with Sun) does not teach (1) a pitch between the first column and the second column is less than about 3 µm. Vanagas et al (see the entire document, in particular, paragraphs [0001], [0013] and [0030]) teaches a process (see paragraph [0001] (method for dicing by laser processing) of Vanagas et al), including providing a pitch between the first column and the second column is less than about 3 µm (see paragraph [0030] (distance between each laser pulse is 1 – 10 µm) of Vanagas et al), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a pitch between the first column and the second column of less than about 3 µm in the process of Ono et al (in combination with Sun) in view of Vanagas et al in order to provide an effective and rapid laser processing method for separating semiconductor devices on a single substrate or separating high thickness, hard and solid substrates (see paragraph [0013] of Vanagas et al). Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al (U.S. Patent Application Publication 2020/0058550 A1) in combination with Sun (U.S. Patent Application Publication 2019/0299329 A1) as applied to claims 8-11 and 15 above, and further in view of Kim et al (U.S. Patent Application Publication 2015/0209898 A1). Regarding claim 13, Ono et al (in combination with Sun) does not teach (1) wherein the focal point of each laser pulse of the first burst is delivered at varying depth within the substrate. Kim et al (see the entire document, in particular, paragraphs [0003], [0021] and [0136]) teaches a process (see paragraph [0003] (method for cutting a material such as glass using a pulsed laser) of Kim et al), wherein the focal point of each laser pulse of the first burst is delivered at varying depth within the substrate (see paragraph [0136] (varying the depth of the focal point in the z-direction) of Kim et al), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deliver each laser pulse of the first burst at a focal point of varying depth within the substrate in the process of Ono et al (in combination with Sun) in view of Kim et al in order to ensure that the cut surface of the brittle material (e.g., glass) is clean (see paragraph [0021] of Kim et al). Claim(s) 14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al (U.S. Patent Application Publication 2020/0058550 A1) as applied to claims 8 and 15 above, and further in view of Xu et al (U.S. Patent Application Publication 2011/0240617 A1). Regarding claim 14, Ono et al does not teach (1) that the laser pulses are either a Bessel beam or a Gaussian beam. Xu et al (see the entire document, in particular, paragraphs [0005], [0013], [0026] and [0134]) teaches a process (see paragraph [0005] (machining materials using pulsed lasers) of Xu et al), wherein the laser pulses are a Gaussian beam (see paragraph [0134] (Gaussian profile) of Xu et al), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the laser pulses as either a Bessel beam or a Gaussian beam in the process of Ono et al in view of Xu et al in order to efficiently machine materials while avoiding mechanically or thermally weakening the material (see paragraph [0013] of Xu et al). Regarding claim 16, see paragraph [0026] (pulse energy of 0.1 – 500 µJ) of Xu et al. Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al (U.S. Patent Application Publication 2020/0058550 A1) in combination with Ota et al (U.S. Patent Application Publication 2016/0318122 A1). Regarding claim 17, Ono et al (see the entire document, in particular, paragraphs [0002], [0018], [0025] and [0038]; Figures 1, 5 and 10) teaches a process (see paragraph [0002] (method of manufacturing a semiconductor device (semiconductors include semiconductor waveguides for optical applications)) of Ono et al), including (a) exposing a substrate to a first plurality of laser pulses at a first location along a dicing path of a respective waveguide combiner, the substrate having a plurality of waveguides, each laser pulse within the first plurality of laser pulses forming a respective void within a first column at the first location to form a plurality of voids (see Figure 1, paragraph [0018] (semiconductor wafer W, chip regions Rchip, dicing regions Rd), Figure 10, paragraph [0038] (modified parts LM (i.e., voids) in modified layer 31), Figure 5, paragraph [0025] (laser oscillator 120 operates laser light 121 in the form of pulses) of Ono et al); and (b) exposing the substrate to a second plurality of laser pulses at a second location along the dicing path of the respective waveguide combiner, each laser pulse within the second plurality of laser pulses forming the respective void within a second column at the second location to form a plurality of voids, the first column and the second column are spaced by a pitch between a center of the first column and the second column along the dicing path (see Figure 1, paragraph [0018] (semiconductor wafer W, chip regions Rchip, dicing regions Rd), Figure 10, paragraph [0038] (modified parts LM (i.e., voids) in modified layer 32; modified layers 31 and 32 are arranged in a plurality of rows at different positions in the thickness direction (z-direction)), Figure 5, paragraph [0025] (laser oscillator 120 operates laser light 121 in the form of pulses) of Ono et al). Ono et al does not teach (1) a non-transitory computer-readable medium storing instructions. Ota et al (see the entire document, in particular, paragraphs [0003] and [0209]) teaches a process (see paragraph [0003] (processing (e.g., dicing) of materials using pulsed lasers) of Ota et al), including a non-transitory computer-readable medium storing instructions (see paragraph [0209] (processing steps or acts of the methods disclosed therein may be implemented in hardware, software or firmware; computer-readable media including non-transitory storage media) of Ota et al), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a non-transitory computer-readable medium storing instructions in the process of Ono et al in view of Ota et al in order to automatically perform the method (see paragraph [0209] of Ota et al). Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al (U.S. Patent Application Publication 2020/0058550 A1) in combination with Ota et al (U.S. Patent Application Publication 2016/0318122 A1) as applied to claim 17 above, and further in view of Sun (U.S. Patent Application Publication 2019/0299329 A1). Regarding claim 18, Ono et al (in combination with Ota et al) does not teach (1) delivering bursts of 5 to 40 laser pulses. Sun (see the entire document, in particular, paragraphs [0001], [0032], [0035], [0036], [0041] and [0068]) teaches a process (see paragraph [0001] (laser micromachining methods) of Sun), including delivering bursts of 5 to 40 laser pulses (see paragraph [0035] (burst 110 may include any number of laser pulses; 3 – 10 laser pulses) of Sun), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deliver bursts of 5 to 40 laser pulses in the process of Ono et al (in combination with Ota et al) in view of Sun in order to process layers of a device without damaging the substrate (see paragraph [0068] of Sun). Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al (U.S. Patent Application Publication 2020/0058550 A1) in combination with Ota et al (U.S. Patent Application Publication 2016/0318122 A1) and Sun (U.S. Patent Application Publication 2019/0299329 A1) as applied to claims 17 and 18 above, and further in view of Vanagas et al (U.S. Patent Application Publication 2017/0250113 A1). Regarding claim 19, Ono et al (in combination with Ota et al and Sun) does not teach (1) providing a pitch between the first column and the second column is less than about 3 µm. Vanagas et al (see the entire document, in particular, paragraphs [0001], [0013] and [0030]) teaches a process (see paragraph [0001] (method for dicing by laser processing) of Vanagas et al), including providing a pitch between the first column and the second column is less than about 3 µm (see paragraph [0030] (distance between each laser pulse is 1 – 10 µm) of Vanagas et al), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a pitch between the first column and the second column of less than about 3 µm in the process of Ono et al (in combination with Ota et al and Sun) in view of Vanagas et al in order to provide an effective and rapid laser processing method for separating semiconductor devices on a single substrate or separating high thickness, hard and solid substrates (see paragraph [0013] of Vanagas et al). Regarding claim 20, see paragraph [0036] (pulse repetition frequency of 100 kHz – 300 MHz) of Sun. Double Patenting The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based e-Terminal Disclaimer may be filled out completely online using web-screens. An e-Terminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about e-Terminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-7 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 12,091,349 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because elimination of an element (i.e., elimination of each of the laser pulses within the first burst having a pulse width of less than about 15 picoseconds and a pulse repetition frequency of greater than about 30 MHz, and elimination of separating a waveguide combiner from the substrate) and its function is obvious if the function of the element is not desired (see MPEP §2144.04(II)(A)). Claims 8-16 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 8-16 of U.S. Patent No. 12,091,349 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because elimination of an element (i.e., elimination of each of the laser pulses within the first plurality of laser pulses having a laser wavelength of about 1.0 to 5 µm and a pulse repetition frequency of greater than about 50 MHz, and elimination of separating a waveguide combiner from the substrate) and its function is obvious if the function of the element is not desired (see MPEP §2144.04(II)(A)). Claims 17-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 17-20 of U.S. Patent No. 12,091,349 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because elimination of an element (i.e., elimination of each of the laser pulses within the first plurality of laser pulses having a laser wavelength of about 1.0 to 5 µm and a pulse repetition frequency of greater than about 50 MHz, and elimination of separating a waveguide combiner from the substrate) and its function is obvious if the function of the element is not desired (see MPEP §2144.04(II)(A)). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEO B. TENTONI whose telephone number is (571)272-1209. The examiner can normally be reached 7:30-4:00 ET M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christina A. Johnson can be reached at (571)272-1176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LEO B. TENTONI Primary Examiner Art Unit 1742 /LEO B TENTONI/Primary Examiner, Art Unit 1742
Read full office action

Prosecution Timeline

Aug 14, 2024
Application Filed
Jan 21, 2026
Non-Final Rejection — §102, §103, §DP
Mar 25, 2026
Interview Requested
Apr 02, 2026
Examiner Interview Summary
Apr 02, 2026
Applicant Interview (Telephonic)

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
92%
With Interview (+9.9%)
2y 11m
Median Time to Grant
Low
PTA Risk
Based on 1386 resolved cases by this examiner. Grant probability derived from career allow rate.

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