DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in the French Republic on 8/17/2023. It is noted, however, that applicant has not filed a certified copy of the FR2308741 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 8/14/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 9 and 20 are objected to because of the following informalities:
Re Claim 9, line 1 references just “the spacer”, wherein it should be, and will be interpreted as, “the spacer structure” for proper antecedent basis.
Re Claim 20, line 2 references “its the entire width”, which appears to be a redundant grammatical typo. For the purposes of examination “its the entire width” will be interpreted simply as “an entire width”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 7, 9-12, 14-15, and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Peidous et al (US 7456058 B1, hereafter Peidous 1) in view of Ishii (US 2009/0174074 A1) and Peidous et al (US 2007/0032024 A1, hereafter Peidous 2).
Re Claim 1, Peidous 1 discloses a transistor (FIG. 8; column 3, line 1 to column 6, line 5), comprising:
a semiconductor layer (142; column 3, line 1);
a stack (144, 150, 172; column 3, line 13 to column 4, line 58) comprising a gate insulator layer (144; column 3, line 13) and a conductive gate (150, 172; column 3, line 46 to column 4, line 58) over the semiconductor layer (142; column 3, line 46 to column 4, line 58);
wherein a length of the conductive gate (150, 172) is smaller on a side of a lower surface of the conductive gate (150, topmost surface, “lower” than upper surface; column 3, line 49), located in a vicinity of the gate insulator layer (144; column 3, line 49), and is greater on a side of an upper surface of the conductive gate (172, bottommost surface, above “lower” surface; column 4, line 61), said upper surface (172, bottommost surface) being opposite to the lower surface (150, topmost surface; column 4, lines 56-66); and
a spacer structure (173, 181, 182; column 5, line 4 to column 6, line 31) adjacent lateral sides of the conductive gate (150, 172; column 5, line 4 to column 6, line 31), said spacer structure (173, 181, 182) comprising a first material (181, 182; column 6, lines 4-5, silicon nitride) at a lower portion of the conductive gate (150; column 6, lines 4-5, at the sides of) where the length of the conductive gate (150, 172) is smaller (column 6, lines 4-5), and a second material (173; column 5, line 11, PSG) at an upper portion of the conductive gate (172; column 5, lines 11-12, at the bottom of) where the length of the conductive gate (150, 172) is greater (column 5, lines 11-12);
Peidous 1 does not explicitly disclose wherein the first material (181, 182, silicon nitride) has a Young’s modulus greater than a Young’s modulus of the second material (173, PSG).
However, Ishii teaches ([0029]) wherein the second material (PSG) has a Young’s modulus of 65 GPa ([0029]).
Additionally, Peidous 2 teaches (FIG. 6; [0016]) wherein the first material (silicon nitride) has a Young’s modulus ([0016], ~350 GPa) greater than a Young’s modulus of the second material ([0016]; PSG, ~65 GPa, taught by Ishii).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Peidous 1 with the limitations taught by Ishii to use CVD as a functionally equivalent blanket depositing technique to result in the second material (Peidous 1: PSG) having a predictable Young’s modulus as taught by Ishii ([0029]). It would also have been obvious to modify the limitations taught by Peidous 1 and Ishii with the limitations taught by Peidous 2 to use a functionally equivalent LPCVD process to result in the first material (Peidous 1: silicon nitride) having a predictable Young’s modulus as taught by Peidous 2 ([0016]).
Re Claim 2, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 1, while Peidous 2 teaches wherein the Young’s modulus of the first material (silicon nitride) is greater than 200 GPa ([0016], ~350 GPa).
No further modification made, see Claim 1 for obviousness statement.
Re Claim 3, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 1, while Ishii teaches wherein the Young’s modulus of the second material (PSG) is smaller than 100 GPa ([0029], ~65 GPa).
No further modification made, see Claim 1 for obviousness statement.
Re Claim 7, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 1, while Peidous 1 further teaches wherein the conductive gate (150, 172) comprises a notch (space between 172 and 144; column 3, line 61) extending across its entire width at the side of the lower surface (150, topmost surface; column 3, lines 42-65).
Re Claim 9, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 7, while Peidous 1 further teaches wherein the first material (181, 182, silicon nitride) of the spacer (173, 181, 182) fills the notch (space between 172 and 144; column 3, lines 42-65, fills in part).
Re Claim 10, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 1, while Peidous 1 further teaches wherein the first material (181, 182, silicon nitride) is based on a material selected from the group consisting of: a nitride (column 6, lines 4-5), a carbide, or diamond.
Re Claim 11, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 1, while Peidous 1 further teaches wherein the second material (173, PSG) is based on a material selected from the group consisting of: tetraethyl-orthosilicate, phosphosilicate glass (column 5, line 11), or silicoboron carbonitride.
Re Claim 12, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 1, while Peidous 1 further teaches wherein the conductive gate (150, 172) comprises a first portion (150; column 4, lines 42-45) defined by the length smaller on the side of the lower surface (150, topmost surface) made of a first gate material (column 3, line 31, refractory metal) and a second portion (172; column 4, lines 56-59) defined by the length greater on the side of the upper surface (172, bottommost surface) made of a second gate material (column 4, line 42, polycrystalline silicon), wherein the second gate material (polycrystalline silicon) is different from the first gate material (refractory metal; column 4, lines 44-47, wherein a different material is used for the two gate electrode layers).
Re Claim 14, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 12, while Peidous 1 further teaches wherein a thickness of the first portion of the conductive gate (150; column 4, lines 42-45, thickness in the direction perpendicular to topmost surface of the semiconductor layer 142) is equal to a thickness of a portion of the spacer structure made of the first material (181, 182; column 6, lines 4-5, largest thickness in the direction perpendicular to topmost surface of the semiconductor layer 142).
Re Claim 15, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 14, while Peidous 1 further teaches wherein a thickness of the second portion of the conductive gate (172; column 4, lines 56-59, thickness in the direction parallel to topmost surface of the semiconductor layer 142) is greater than a thickness of a portion of the spacer structure made of the second material (173; column 5, line 11, thickness in the direction parallel to topmost surface of the semiconductor layer 142).
Re Claim 18, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 1, while Peidous 1 further teaches wherein the transistor further comprises an insulating liner (160; column 3, line 61) extending along a side surface of the conductive gate (150, 172; column 3, line 61) and on an upper surface of the gate insulator layer (160) in a notch region (space between 172 and 144; column 3, line 61) where the length of the conductive gate (150, 172) is smaller on the side of the lower surface of the conductive gate (150, topmost surface; column 3, line 61).
Re Claim 19, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 1, while Peidous 1 further teaches wherein said length of the conductive gate (150, 172) being smaller on the side of the lower surface of the conductive gate (150, topmost surface), and greater on the side of the upper surface of the conductive gate (172, bottommost surface) forms a notch (space between 172 and 144; column 3, line 61), and wherein a separation between the first material (181, 182, silicon nitride) and the second material (173, PSG) is located at a level of an upper wall of the notch (space between 172 and 144) in the conductive gate (150, 172; column 3, line 61, 181/182 and 173 meet at one point at bottom surface of 172).
Re Claim 20, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 19, while Peidous 1 further teaches wherein the notch (space between 172 and 144) in the conductive gate (150, 172) extends across its the entire width of the conductive gate (150, 172) at the side of the lower surface (150, topmost surface; column 3, lines 42-65).
Re Claim 21, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 19, while Peidous 1 further teaches wherein the first material (181, 182, silicon nitride) is located only in the notch (space between 172 and 144) formed in the conductive gate layer (150, 172; column 3, line 61).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Peidous 1, Ishii, and Peidous 2, as applied to Claim 1, in view of Li et al (US 2022/0157710 A1, hereafter Li) and Guo (US 6596599 B1).
Re Claim 4, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 1, but they do not explicitly disclose wherein the first material (Peidous 1: 181, 182, silicon nitride) has a dielectric constant greater than a dielectric constant of the second material (Peidous 1: 173, PSG).
However, Li teaches ([0049]) wherein the second material (PSG) has a dielectric constant of at/less than about 3.9 ([0049]).
Additionally, Guo teaches wherein the first material (silicon nitride) has a dielectric constant (column 5, line 60, 7.4) greater than a dielectric constant of the second material (column 5, line 60; PSG, <~3.9, taught by Li).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the transistor as discussed with regards to Claim 1 above with the limitations taught by Li to have used CVD as a functionally equivalent blanket depositing technique to result in the second material (Peidous 1: PSG) having a predictable dielectric constant as taught by Li ([0049]). It would also have been obvious to modify the transistor as discussed with regards to Claim 1 above and the limitations taught by Li with the limitations taught by Guo to use a functionally equivalent LPCVD process to result in the first material (Peidous 1: silicon nitride) having a predictable dielectric constant as taught by Guo (column 5, line 60, 7.4).
Re Claim 5, Peidous 1, Ishii, Peidous 2, Li, and Guo teach the transistor according to Claim 4, while Guo teaches wherein the dielectric constant of the first material (silicon nitride) is greater than 7 (column 5, line 60, 7.4).
No further modification made, see Claim 4 for obviousness statement.
Re Claim 6, Peidous 1, Ishii, Peidous 2, Li, and Guo teach the transistor according to Claim 4, while Li teaches wherein the dielectric constant of the second material (PSG) is smaller than 4 ([0049], <~3.9).
No further modification made, see Claim 4 for obviousness statement.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Peidous 1, Ishii, and Peidous 2, as applied to Claim 7, in view of Shank et al (US 2018/0269295 A1, hereafter Shank).
Re Claim 8, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 7, but they do not explicitly disclose wherein a difference between a length of the conductive gate (Peidous 1: 150, 172) at the side of the lower surface and a length of the conductive gate (Peidous 1: 150, 172) at the side of the upper surface on the upper surface is in a range from 5 nm to 40 nm.
However, Shank discloses a transistor comprising wherein a difference between a length of the conductive gate (34, 36; [0020]) at the side of the lower surface (36, w2; [0021], 0.08 microns) and a length of the conductive gate (34, 36) at the side of the upper surface (34, w1; [0021], 0.09 microns) on the upper surface is in a range from 5 nm to 40 nm ([0021]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the transistor as discussed with regards to Claim 7 above with the limitations taught by Shank to utilize a functionally equivalent T-shaped gate electrode structure with specificized dimensions for optimization of parasitic resistance and capacitance as taught by Shank ([0033]).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Peidous 1, Ishii, and Peidous 2, as applied to Claim 1, in view of Nishihori et al (US 2017/0213848 A1, hereafter Nishihori).
Re Claim 22, Peidous 1, Ishii, and Peidous 2 teach the transistor according to Claim 1, but they do not explicitly disclose a radio frequency switch comprising said transistor.
However, Nishihori discloses a radio frequency switch (FIG. 2; [0028]-[0040]) comprising a transistor ([0031], specifically a MOSFET).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the transistor as discussed with regards to Claim 1 above with the limitations taught by Nishihori to utilize a MOSFET in a radio frequency device to switch paths of radio frequency signals as taught by Nishihori ([0025]).
Allowable Subject Matter
Claims 13 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re Claim 13, the prior art cannot anticipate, or render obvious, the limitations of: wherein the first gate material is made of polysilicon and the second gate material is made of germanium-doped polysilicon, in combination with the additionally claimed features of Claim 13.
Re Claim 16, the prior art cannot anticipate, or render obvious, the limitations of: wherein a thickness of the first portion of the conductive gate is less than a thickness of a portion of the spacer structure made of the first material, in combination with the additionally claimed features of Claim 16.
In Re Claim 17, it is objected to due to its dependence from Claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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