DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-6, 11, 14-15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 2019/0296751) in view of Maki (JP H089257A).
Regarding claim 1, Zhang discloses a structure [fig. 10] comprising: three transistors [1020, 1010, 1030 in fig. 10] including: a first transistor [1020] with a first front gate [front gate 1020] and a first back gate [back gate 1020]; a second transistor [1010] with a second front gate [front gate 1010] and a second back gate [front gate 1010]; and a third transistor [1030] with a third front gate [front gate 1030] and a third back gate [front gate 1030], wherein the first transistor is connected in series between the second transistor and the third transistor, wherein the first back gate, the second back gate, and the third back gate are connected to receive a first control voltage [EN] , and wherein the second front gate and the third front gate are connected to receive a second control voltage [EN].
Zhang differs from the claim in that the first transistor [1020] front gate receives ground rather than the claimed first control signal, and the second and third transistor front gate receives [EN] rather than the second control signal.
However, Zhang teaches that EN is asserted low [EN= 0V] during the OFF state of the circuit [see par. 0066]. A low EN signal therefor functional as a conventional disable signal. The claimed “first control signal” likewise serves as a disable signal applied to the front of first transistor and back gates of the first, second and third transistors in the OFF state. Similarly, Zhang teaches that EN is driven high (e.g., 0.8V) during the enable state [par. 0070-0072]. A high EN signal therefore functions as an enable type control voltage. The claimed “second control voltage” is likewise an enable signal applied to the front gates of the second and third transistor. It would have been obvious to person of ordinary skill in the art to modify the gate connections of Zhang to apply the first control signal to the back gates of all three transistors and the second control voltage on the front gates of second and third transistors is a predictable design choice yielding no unexpected results.
Zhan further teaches wherein the first transistor shared a first source/drain region with the second transistor; and also shares a second source/drain region with the third transistor (as shown at locations 1003 and 1004 respectively, see fig. 10). Zahn further teaches that capacitance is present at these shared source/drain regions (locations 1003 and 1004, par. 0067). Zhan does not disclose a first capacitor and a second capacitor connected to the nodes of the first and second shared source/drain region.
However, Maki discloses [fig. 1] a first capacitor [C1] connected to a first shared source/drain region [N1] between a first transistor [M2] and a second transistor [M1]; and a second capacitor [C2] connected to a second shared source/drain region [N2] between the first transistor and a third transistor [M3]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Zhan in by adding the capacitors at the shared source/drain region as taught in Maki in order to suppress the fluctuation of the boosted voltage that is caused by a power voltage [abstract].
Regarding claim 2, Zhang in view of Maki discloses [see fig. 1] wherein the second transistor is connected between a ground rail [ground] and the first transistor and the third transistor is connected between the first transistor and the ground rail.
Regarding claim 5, Zhang in view of Maki discloses [see fig. 1] wherein the first capacitor includes first capacitor plates connected to the first shared source/drain region and a first voltage line [voltage line at ϕ1], respectively, and wherein the second capacitor includes second capacitor plates connected to the second shared source/drain region and a second voltage line [voltage line at ϕ2], respectively.
Regarding claim 6, Zhang in view of Maki discloses [see fig. 10] wherein the three transistors are N-type field effect transistors [NFETs, par. 0062], wherein the first control voltage and the second control voltage are concurrently switchable between high and low voltage levels to concurrently switch the three transistors between on and off states, wherein the high and low voltage levels of the first control voltage are at a first positive voltage level and 0.0V, respectively, wherein the first positive voltage level is higher than threshold voltages of any of the three transistors and at 0.0 volts, wherein the high and low voltage levels of the second control voltage are at the first positive voltage level and at a second positive voltage level, respectively, and wherein the second positive voltage level is lower than the first positive voltage level and higher than 0.0V [par. 0061-0075].
Regarding claim 11, Zhang discloses a structure [fig. 10] comprising: a first voltage line [915, figs. 9 and 10]; a second voltage line [916, figs. 9 and 10]; and a capacitive element [920, fig. 9, par. 0062], wherein the capacitive element includes: three transistors [1020, 1010 and 1030] including: a first transistor [1020] with a first front gate and a first back gate; a second transistor [1010] with a second front gate and a second back gate; and a third transistor [1030] with a third front gate and a third back gate, wherein the first transistor is connected in series between the second transistor and the third transistor, wherein the first back gate, the second back gate and the third back gate are connected to receive a first control voltage [EN], and wherein the second front gate and the third front gate are connected to receive a second control voltage [EN].
Zhang differs from the claim in that the first transistor [1020] front gate receives ground rather than the claimed first control signal, and the second and third transistor front gate receives [EN] rather than the second control signal.
However, Zhang teaches that EN is asserted low [EN= 0V] during the OFF state of the circuit [see par. 0066]. A low EN signal therefor functional as a conventional disable signal. The claimed “first control signal” likewise serves as a disable signal applied to the front of first transistor and back gates of the first, second and third transistors in the OFF state. Similarly, Zhang teaches that EN is driven high (e.g., 0.8V) during the enable state [par. 0070-0072]. A high EN signal therefore functions as an enable type control voltage. The claimed “second control voltage” is likewise an enable signal applied to the front gates of the second and third transistor. It would have been obvious to person of ordinary skill in the art to modify the gate connections of Zhang to apply the first control signal to the back gates of all three transistors and the second control voltage on the front gates of second and third transistors is a predictable design choice yielding no unexpected results.
Zhan further teaches wherein the first transistor shared a first source/drain region with the second transistor; and also shares a second source/drain region with the third transistor (as shown at locations 1003 and 1004 respectively, see fig. 10). Zahn further teaches that capacitance is present at these shared source/drain regions (locations 1003 and 1004, par. 0067). Zhan does not disclose a first capacitor and a second capacitor connected to the nodes of the first and second shared source/drain region and the second transistor being connected between a ground rail and the first transistor and the third transistor being connected between the first transistor and the ground rail
However, Maki discloses [fig. 1] a first capacitor [C1] connected between a first voltage line [ϕ1] and a first shared source/drain region [N1] between a first transistor [M2] and a second transistor [M1]; and a second capacitor [C2] connected between a second voltage line [ϕ2] and a second shared source/drain region [N2] between the first transistor and a third transistor [M3] and the second transistor being connected between a ground rail [ground] and the first transistor and the third transistor being connected between the first transistor and the ground rail. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Zhan in by adding the capacitors at the shared source/drain region as taught in Maki in order to suppress the fluctuation of the boosted voltage that is caused by a power voltage [abstract].
Regarding claim 14, Zhang in view of Maki discloses [see fig. 1] wherein the first capacitor includes first capacitor plates connected to the first shared source/drain region and the first voltage line, respectively, and wherein the second capacitor includes second capacitor plates connected to the second shared source/drain region and the second voltage line, respectively.
Regarding claim 15, Zhang in view of Maki discloses [see fig. 10] wherein the three transistors are N-type field effect transistors, and wherein the first control voltage and the second control voltage are concurrently switchable between high and low voltage levels to concurrently switch the three transistors between on and off states.
Regarding claim 20, Zhang discloses a structure [fig. 10] comprising: a first voltage line [915, figs. 9 and 10]; a second voltage line [916, figs. 9 and 10]; multiple capacitive elements [920, fig. 10] connected in parallel between the first voltage line and the second voltage line, wherein each capacitive element includes: three transistors [1020, 1010 and 1030] including: a first transistor [1020] with a first front gate and a first back gate; a second transistor [1010] with a second front gate and a second back gate; and a third transistor [1030] with a third front gate and a third back gate, wherein the first transistor is connected in series between the second transistor and the third transistor, wherein the first back gate, the second back gate and the third back gate of the capacitive element are connected to receive a first control voltage [EN], and wherein the second front gate and the third front gate of the capacitive element are connected to receive a second control voltage [EN].
Zhang differs from the claim in that the first transistor [1020] front gate receives ground rather than the claimed first control signal, and the second and third transistor front gate receives [EN] rather than the second control signal.
However, Zhang teaches that EN is asserted low [EN= 0V] during the OFF state of the circuit [see par. 0066]. A low EN signal therefor functional as a conventional disable signal. The claimed “first control signal” likewise serves as a disable signal applied to the front of first transistor and back gates of the first, second and third transistors in the OFF state. Similarly, Zhang teaches that EN is driven high (e.g., 0.8V) during the enable state [par. 0070-0072]. A high EN signal therefore functions as an enable type control voltage. The claimed “second control voltage” is likewise an enable signal applied to the front gates of the second and third transistor. It would have been obvious to person of ordinary skill in the art to modify the gate connections of Zhang to apply the first control signal to the back gates of all three transistors and the second control voltage on the front gates of second and third transistors is a predictable design choice yielding no unexpected results.
Zhan further teaches wherein the first transistor shared a first source/drain region with the second transistor; and also shares a second source/drain region with the third transistor (as shown at locations 1003 and 1004 respectively, see fig. 10). Zahn further teaches that capacitance is present at these shared source/drain regions (locations 1003 and 1004, par. 0067). Zhan does not disclose a first capacitor and a second capacitor connected to the nodes of the first and second shared source/drain region and the second transistor being connected between a ground rail and the first transistor and the third transistor being connected between the first transistor and the ground rail
However, Maki discloses [fig. 1] a first capacitor [C1] connected between a first voltage line [ϕ1] and a first shared source/drain region [N1] between a first transistor [M2] and a second transistor [M1]; and a second capacitor [C2] connected between a second voltage line [ϕ2] and a second shared source/drain region [N2] between the first transistor and a third transistor [M3] and the second transistor being connected between a ground rail [ground] and the first transistor and the third transistor being connected between the first transistor and the ground rail. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Zhan in by adding the capacitors at the shared source/drain region as taught in Maki in order to suppress the fluctuation of the boosted voltage that is caused by a power voltage [abstract].
Claims 3, 9-10, 12, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Maki.
Regarding claims 3 and 12, Zhang in view of Maki discloses all the features with respect to claims 1 and 11 and as indicated above. Zhang in view of Maki does not explicitly disclose wherein the first transistor has a larger total channel width than the second transistor and a larger total channel width than the third transistor. The person of ordinary skill in the art would have been motivated to modify Zhang in view of Maki in the above manner for the purpose of providing suitable dimension of the transistor structure. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claims 9 and 18, Zhang in view of Maki discloses all the features with respect to claims 1 and 11 and as indicated above. Zhang in view of Maki does not explicitly disclose wherein the first capacitor and the second capacitor are any of metal-oxide-metal capacitors and metal-insulator-metal capacitors and wherein the first capacitor and the second capacitor are completely offset from the three transistors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to select a metal-oxide-metal capacitors and metal-insulator-metal capacitors would have been an obvious design choice because these capacitor types are standard, widely used, and specifically intended for integration separate from transistor active regions. Thus, it would have been obvious to implement the first and second capacitor as metal-oxide-metal capacitors and metal-insulator-metal capacitors and to position them completely offset from the three transistors to achieve predictable benefits such as reduced substrate noise and improved layout flexibility.
Regarding claims 10 and 19, Zhang in view of Maki discloses all the features with respect to claims 1 and 11 as indicated above. Zhang in view of Maki does not explicitly disclose wherein the first capacitor and the second capacitor are any of metal-oxide-metal capacitors and metal-insulator-metal capacitors at least partially overlaying at least the second transistor and the third transistor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to select a metal-oxide-metal capacitors and metal-insulator-metal capacitors would have been an obvious design choice because these capacitor types are standard in CMOS processes and are specifically intended to be fabricated in the metal layers above the transistor layer. It would therefore have been obvious to implement the first and second capacitor as metal-oxide-metal capacitors and metal-insulator-metal capacitors and to position them such that they at least partially overlay the second and third transistors, in order to predictable benefits such as reduced die area and increased capacitance density without altering the underlying transistor layout.
Allowable Subject Matter
Claims 4, 7-8, 13 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/METASEBIA T RETEBO/ Primary Examiner, Art Unit 2842