Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed July 7, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 8, 14
b. Pending: 1-20
Claims 1, 4, 8, 12, 14, 16, 19, and 20 have been amended.
Drawings
The objection to Fig. 8 is withdrawn pursuant to replacement sheet. Examiner acknowledges additional replacement sheet for Fig. 1B.
The drawings are objected to because Figs. 2A, 2B, 2C, 2D, 3 appear blurry and the alphanumeric labels are therefore not fully legible. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The amendments to the Specification have been reviewed and are accepted by
the Examiner. The objections to the Specification are withdrawn.
Claim Objections
The claim objections are withdrawn pursuant to claim amendments.
Claim Rejections - 35 USC § 112
The 112(b) claim rejections are withdrawn pursuant to claim amendments.
Response to Arguments
Applicant's arguments filed July 7, 2026 have been fully considered but they are not persuasive.
Regarding the 102 rejection, Applicant’s argument on p.12 that Hossain (US Pub. 20180248577 A1) does not teach the new limitation of claim 1 is persuasive because Hossain does not teach sampling of the same data signal at interleaved time intervals. However, Kim (US Pub. 20240430140 A1) does teach the new limitation; see 103 rejection of claim 1 below.
Regarding the 103 rejection, Examiner agrees with the statement on p.14 that “None of these references is cited for, nor does any of them teach, multiple data detector circuits that generate detected bit values based on samples of the same data signal taken at interleaved time intervals.” However, Hossain teaches two data detectors, and Examiner has used Kim in combination with Hossain to teach the last limitation of claim 1, which only teaches one data detector (the “second data detector”). Per MPEP §2141 Part III, “The prior art reference (or references when combined) need not teach or suggest all the claim limitations. However, Office personnel must explain why the difference(s) between the prior art and the claimed invention would have been obvious to one of ordinary skill in the art.” Examiner asserts that in addition to the reasoning provided below, it would have been obvious to combine Kim with Hossain because they both aim to compensate for ISI in DFE circuits (Hossain para. [0030], Kim para. [0119]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6-8, 10, 14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain (US Pub. 20180248577 A1) in view of Kim (US Pub. 20240430140 A1).
Regarding independent claim 1, Hossain discloses a system comprising:
a memory sub-system controller (Fig. 2: memory controller 210; [0046]) to transmit a data signal ([0049]: A memory controller, such as memory controller 210, manages the flow of data going to and from memory devices, such as memory 220) via a communication channel (Fig. 1: interconnect system 140; [0044]: channel (e.g., interconnect system 140); [0047]: one or more of drivers 213 of memory controller 210 may correspond to transmitter circuit 110. Examiner concludes that interconnect system 140 of Fig. 1 is analogous to the channel between the memory controller 210 and memory 220 of Fig. 2);
a receiver (Fig. 2: memory 220; [0046]) to receive the data signal from the memory sub-system controller ([0046]: Receivers 224 of memory 220 may receive one or more of the Q[1:N] signals from memory controller 210) via an interface ([0050]: signal ports Q[1:N] on memory controller 210 and memory 220 may correspond to pins such as CS (chip select), a command interface that includes timing control strobes…), the receiver comprising a decision feedback equalizer (DFE) sub-system (Fig. 3A: receiver 300; [0051]: FIG. 3A illustrates a non-speculative DFE four-level pulse amplitude modulation (PAM-4) receiver with analog feed-forward equalization (FFE); [0048]: The one or more of receivers 224 of memory 220 may use a DFE architecture that uses the current input voltage (symbol) received from memory controller 210 as an input to help determine a DFE feedback signal), the DFE sub-system comprising:
a first data detector circuit (Fig. 2: a receiver 224; [0051]) comprising a first tap circuit (Fig. 3A: sampler 321; [0052]), wherein the first data detector circuit generates, using a first reference voltage (reference voltage Vref1; [0056]), a first subset of detected bit values (decision bit OUT[1]; [0148]) corresponding to the data signal ([0070]: sampler 520 is a PAM-4 sampler (e.g., similar to, or the same as, PAM-4 sampler 320 or 420) and outputs a plurality of decision bits accordingly); and
a second data detector circuit (Fig. 2: a different receiver 224; [0048]: one or more of receivers 224. Examiner concludes that the memory 220 may include many receivers 224, each of which has a DFE architecture) comprising a second tap circuit (a sampler (e.g.: 322) of the different receiver 224), wherein the second data detector circuit generates a second subset of detected bit values (decision bit output, e.g. OUT[2] of the different receiver 224) corresponding to the data signal ([0070]) using a second reference voltage (reference voltage e.g.: Vref2 of the different receiver 224),
Hossain does not disclose:
wherein the first subset and the second subset of detected bit values are based on samples of the data signal taken at interleaved time intervals.
However, Kim teaches:
wherein the first subset (Fig. 7B: first bit SDS11; [0075]: the first slicer 441 may generate a first bit SDS11 of the sampled signal SDS1 by sampling the first bit CDS11 of the compensated data signal CDS1 based on the first divided strobe signal DQS_2N_0) and the second subset of detected bit values (second bit SDS12; [0075]) are based on samples of the data signal taken at interleaved time intervals ([0075]: The second slicer 442 may generate a second bit SDS12 of the sampled signal SDS1 by sampling the second bit CDS12 of the compensated data signal CDS1 based on the third divided strobe signal DQS_2N_180, which may be 180° out-of-phase relative to the first divided strobe signal DQS_2N_0. Examiner asserts that a strobed sampling of a first bit and a strobed sampling of a second bit that are 180° out-of-phase relative to each other are analogous to interleaved time intervals because the sampling of the first bit alternates timing with the sampling of the second bit. Examiner notes that both subsets of detected bit values are based on samples of the same data signal. Also refer to Fig. 9A, lines DQS_2N_0 and DQS_2N_180, which corresponds to the clocks associated with first bit SDS11 and the second bit SDS12, see annotated screenshot below. Also see [0093]).
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It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to Hossain wherein the first subset and the second subset of detected bit values are based on samples of the data signal taken at interleaved time intervals in order to provide a receiver that increases operating speed and reduces power consumption (Kim, [0005]).
Regarding claim 3, Hossain and Kim together disclose the limitations of claim 1, and further through Hossain:
wherein the first reference voltage is different from the second reference voltage ([0056]: Reference voltages Vref1, Vref2, and Vref3 are typically selected to be between PAM-4 voltage levels. For example, if the four PAM-4 levels are −3V, −1V, +1V, and +3V, Vref1 may be selected to be −2V, Vref2=0V, and Vref3=+2V).
Regarding claim 6, Hossain and Kim together disclose the limitations of claim 1. Hossain does not explicitly disclose:
wherein the receiver comprises a memory device comprising an array of memory cells.
However, Kim teaches:
wherein the receiver (Fig. 5: semiconductor memory device 200; [0048]; [0008]: a semiconductor memory device includes a receiver and a control logic circuit. The receiver is connected to a memory controller through a channel, and generates an output data based on a data signal received from the channel. The control logic circuit controls the receiver. Examiner concludes that the semiconductor memory device 200 is a receiver) comprises a memory device comprising an array of memory cells ([0048]: the semiconductor memory device 200 may include…a memory cell array 310…the semiconductor memory device 200 may be a volatile memory device, such as a dynamic random access memory (DRAM) device).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified Hossain wherein the receiver comprises a memory device comprising an array of memory cells in order to provide a receiver that increases operating speed and reduces power consumption (Kim, [0005]).
Regarding claim 7, Hossain and Kim together disclose the limitations of claim 6. Further through Kim:
wherein the data signal comprises data to be programmed to at least a portion of the array of memory cells ([0037]: based on requests from a host (not illustrated), the memory controller 100 may store data (e.g., write or program data) into the semiconductor memory device 200, or may retrieve data (e.g., read or sense data) from the semiconductor memory device 200; [0038]: The memory controller 100…may exchange a data signal DS with the semiconductor memory device 200 via the data I/O lines).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified Hossain wherein the data signal comprises data to be programmed to at least a portion of the array of memory cells in order to provide a receiver that increases operating speed and reduces power consumption (Kim, [0005]).
Independent claim 8 contains a second, third, and fourth limitation that are substantially the same in claimed subject matter as limitations of claim 1, except for being drafted with a focus on a device instead of a system, and those limitations are thus rejected for the same reasons using Hossain.
Hossain does not disclose:
A memory device comprising:
a memory array comprising a set of memory cells; and
However, Kim teaches:
A memory device (Fig. 5: semiconductor memory device 200; [0048]) comprising:
a memory array (memory cell array 310; [0048]) comprising a set of memory cells ([0049]: Each of the first through eighth bank arrays 310a˜380h may include a plurality of memory cells MC formed at intersections of a plurality of word-lines WL and a plurality of bit-line BTL); and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to Hossain wherein a memory device comprises a memory array that comprises a set of memory cells in order to provide a receiver that increases operating speed and reduces power consumption (Kim, [0005]).
Regarding claim 10, Hossain and Kim together disclose the limitations of claim 8. Claim 10 contains exactly the same limitations as claim 3, and is thus rejected for the same reasons.
Independent claim 14 contains limitations that are substantially the same in claimed subject matter as limitations of claim 1, except for being drafted in method format, and is thus rejected for the same reasons using Hossain.
Regarding claim 17, Hossain and Kim together disclose the limitations of claim 14. Claim 17 contains exactly the same limitations as claim 3, and is thus rejected for the same reasons.
Claims 2, 9, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain (US Pub. 20180248577 A1) and Kim (US Pub. 20240430140 A1) as applied to claims 1, 8, and 14 above, respectively, and further in view of Xie et al. (US Pat. 9542991 B1; “Xie”).
Regarding claim 2, Hossain and Kim together disclose the limitations of claim 1. Neither Hossain nor Kim discloses:
wherein the DFE sub-system further comprises one or more reference voltage generation circuits to generate the first reference voltage and the second reference voltage.
However, Xie teaches:
wherein the DFE sub-system (Fig. 3: registered clock driver (RCD) circuit 100; col. 6, lines 6-7: The circuit 102 may implement a decision feedback equalization (DFE) circuit. Examiner concludes that RCD circuit 100 is analogous to a DFE sub-system because it contains a DFE circuit) further comprises one or more reference voltage generation circuits (reference voltage (VREF) generation circuit 104; col. 6, lines 54-55) to generate the first reference voltage and the second reference voltage (col. 6, lines 54-61: The circuit 104 may implement a reference voltage (VREF) generation circuit. The VREF circuit 104 may be operational to provide a fixed reference voltage in the signal VREF to multiple (e.g., up to 33) copies of the DFE circuit 102. In some embodiments, the signal VREF may be generated as a fraction (e.g., half) of the input/output voltage domain VDDIO. Other reference voltages may be generated to meet the design criteria of a particular implementation).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Xie to Hossain wherein the DFE sub-system further comprises one or more reference voltage generation circuits to generate the first reference voltage and the second reference voltage in order to reduce power consumption and inter-symbol interference (Xie, col. 2, lines 7-17).
Regarding claim 9, Hossain and Kim together disclose the limitations of claim 8. Claim 9 contains exactly the same limitations as claim 2, and is thus rejected for the same reasons.
Regarding claim 15, Hossain and Kim together disclose the limitations of claim 14. Claim 15 contains substantially the same limitations as claim 2, and is thus rejected for the same reasons.
Claims 4-5, 12-13, 16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain (US Pub. 20180248577 A1) and Kim (US Pub. 20240430140 A1) as applied to claims 1, 8 and 14 above, respectively, and further in view of Sato (JP 2004297536 A).
Regarding claim 4, Hossain and Kim together disclose the limitations of claim 1. Hossain does not disclose:
wherein the first data detector circuit comprises a tap voltage generation circuit to generate a first tap voltage to control a first tap switch of the first tap circuit of and a second tap voltage to control a second tap switch of the first tap circuit of the first data detector circuit.
However, Sato teaches:
wherein the first data detector circuit (Fig. 2: multi-training adaptive equalization circuit; para. [0025] on page 6, line 8) comprises a tap voltage generation circuit ([0023]: training/data equalization switching control unit 23) to generate a first tap voltage to control a first tap switch of the first tap circuit and a second tap voltage to control a second tap switch of the first tap circuit ([0023]: The training/data equalization switching control unit 23 controls the switching of the FF filter input signal selector 12 and the FB filter input signal selector 20. Examiner asserts that the FF filter input signal selector 12 and the FB filter input signal selector 20 are analogous to the first and second tap switches) of the first data detector circuit (Fig. 2), wherein the first data detector circuit (Fig. 2) comprises the first (FF filter input signal selector 12) and second tap switches (FB filter input signal selector 20).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Sato to modified Hossain wherein the first data detector circuit comprises a tap voltage generation circuit to generate a first tap voltage to control a first tap switch of the first tap circuit and a second tap voltage to control a second tap switch of the first tap circuit of the first data detector circuit, wherein the first data detector circuit comprises the first and second tap switches in order to improve transmission by reducing equalization errors (Sato, [0012]).
Regarding claim 5, Hossain, Kim, and Sato together disclose the limitations of claim 4. Further, through Sato:
wherein the tap voltage generation circuit (Fig. 3: data determination unit 113, training signal generator 114, and switch 115; [0003] & [0007]) is arranged in parallel to a first path corresponding to the data signal (the signal from the complex adder 112; [0007]: The data determination unit 113 selects a single mapping value corresponding to a signal point (mapping value) that receives a signal from the complex adder 112. This output signal is output as demodulated data. Examiner asserts that the data signal and tap signal have parallel paths; see annotated screenshot below).
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It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Sato to modified Hossain wherein the tap voltage generation circuit is arranged in parallel to a first path corresponding to the data signal in order to improve transmission by reducing equalization errors (Sato, [0012]).
Regarding claim 12, Hossain and Kim together disclose the limitations of claim 8. Claim 12 contains exactly the same limitations as claim 4, and is thus rejected for the same reasons.
Regarding claim 13, Hossain, Kim, and Sato together disclose the limitations of claim 12. Claim 13 contains exactly the same limitations as claim 5, and is thus rejected for the same reasons.
Regarding claim 16, Hossain and Kim together disclose the limitations of claim 14. Claim 16 contains substantially the same limitations as part of claim 4, and is thus rejected for the same reasons.
Regarding claim 19, Hossain and Kim together disclose the limitations of claim 14. Claim 19 contains substantially the same limitations as part of claim 4, and is thus rejected for the same reasons.
Regarding claim 20, Hossain, Kim, and Sato together disclose the limitations of claim 19. Claim 20 contains exactly the same limitations as claim 5, and is thus rejected for the same reasons.
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain (US Pub. 20180248577 A1) and Kim (US Pub. 20240430140 A1) as applied to claims 8 and 14 above, respectively, and further in view of Furutani (US Pat. 5926051 A).
Regarding claim 11, Hossain and Kim together disclose the limitations of claim 8. Neither Hossain nor Kim discloses:
wherein the first reference voltage and the second reference voltage cancel an offset between the first data detector circuit and the second data detector circuit.
However, Furutani teaches:
wherein the first reference voltage (
V
C
C
+
3
V
T
H
; col. 3, lines 25-27: an output signal
φ
E
1
of a H level is output when high voltage
V
P
P
becomes lower than
V
C
C
+
3
V
T
H
) and the second reference voltage (
V
C
C
+
2
V
T
H
; col. 3, lines 34-41: the second detector provides an output signal
φ
E
2
of a H level when high voltage
V
P
P
becomes lower than
V
C
C
+
2
V
T
H
) cancel an offset between the first data detector circuit (Fig. 8: transistors Q34-Q36 and Q41-Q45) and the second data detector circuit (second data detector is Fig. 8: transistors Q37-Q39 and Q46-Q48; col. 2, line 58 – col. 3, line 6: When high voltage
V
P
P
supplied to a word line driver 139 becomes lower than a predetermined potential, first detector 131 provides an output signal .phi..sub.E1 of a H level to first oscillator 134…Small pump 136 responds to this oscillation signal to provide high voltage
V
P
P
to word line driver 139 at a standby state. When the high voltage supplied to word line driver 139 becomes lower than a predetermined potential, second detector 132 provides an output signal .phi..sub.E2 of H level to second oscillator 135…Large pump 137 responds to this oscillation signal to rapidly increase high voltage
V
P
P
supplied to word line driver 139; col. 11, lines 39-43: the level of high voltage
V
P
P
becomes
V
C
C
+
2
V
T
H
P
at the time of standby, and
V
C
C
-
∆
V
+
2
V
T
H
P
at the time of an active state, allowing reduction in the difference therebetween. Therefore, variation in the level of high voltage
V
P
P
can be reduced).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Furutani to modified Hossain wherein the first reference voltage and the second reference voltage cancel an offset between the first data detector circuit and the second data detector circuit in order to reduce power consumption of a device without increasing the soft error rate (Furutani, col. 5, lines 3-10).
Regarding claim 18, Hossain and Kim together disclose the limitations of claim 14. Claim 18 contains substantially the same limitations as claim 11, and is thus rejected for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Fortin et al. (US Pat. 11356304 B1): col. 13, lines 34 through 51 and Fig. 10 are relevant to claims 1, 8, and 14.
Tajalli (US Pub. 20190182081 A1): para. [0070] and Fig. 4 are relevant to claims 1, 8, and 14.
Woo et al. (US Pub. 20230033286 A1): paras. [0125]-[0130] and Figs. 8 & 9 are relevant to claims 1, 8, and 14.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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/E.R.A./Examiner, Art Unit 2824
/SULTANA BEGUM/Primary Examiner, Art Unit 2824
9/15/2026
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