DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statements filed on 08/14/2024, 04/30/2025 and 12/18/2025 have been considered.
Drawings
The drawings filed on 08/14/2024 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 08/14/2024 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 9 and 10 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Jang ((US 2015/0920394).
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Regarding claim 1, Jang (US 2015/0920394) discloses:
A method for fabricating a semiconductor package, comprising:
forming a first molding layer (150, ¶0074) covering sidewalls of the substrate (120, ¶0074);
providing a first semiconductor chip (220, ¶0075) on a first surface of the substrate (120) and a second surface of the first molding layer 150); and
forming a second molding layer (250, ¶0091) directly on the substrate (120) and the first molding layer 9150), covering sidewalls of the first semiconductor chip (220), wherein the first semiconductor chip (220) includes a first region and a second region, wherein the first region vertically overlaps with the substrate (120), and wherein the second region vertically overlaps with the first molding layer (150).
Regarding claim 3, Jang further discloses:
forming an underfill layer between the substrate and the first semiconductor chip and between the first molding layer and the first semiconductor chip.
Regarding claim 9, Jang further discloses:
forming a plurality of first bumps (232, ¶0075) between the substrate (120) and the first semiconductor chip (220); and
forming an underfill layer (240, ¶0078) covering the first bumps between the first semiconductor chip (220) and the substrate (120), and between the first semiconductor chip (220) and the first molding layer (150).
Regarding claim 10, Jang further discloses:
forming an underfill layer (240) disposed between the substrate (120) and the first semiconductor chip (220), wherein, an end of the underfill layer (240) is spaced apart from the interposer substrate (120).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang.
Regarding claim 8, Jang discloses:
disposing a second semiconductor chip (420) on a first surface of the substrate (120), wherein, the second semiconductor chip (420) at least partially overlaps the substrate (120). Jang does not disclose “disposing a second semiconductor chip on a first surface of the substrate and located side by side with the first semiconductor chip.
However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art method would not be executed differently if modified to the claimed shape or size. Therefore, the claimed limitations are considered met.
Regarding claim 19, Jang discloses:
A method for fabricating a semiconductor package, comprising:
forming a first molding layer (150) covering sidewalls of the interposer substrate (120);
mounting a first semiconductor chip (220) and a second semiconductor chip (420, ¶0095) spaced apart from the first semiconductor chip (220), on the interposer substrate, wherein the first semiconductor chip (220) has a mounting region that vertically overlaps with the interposer substrate and an overhang region that vertically overlaps with the first molding layer;
forming first bumps (232, ¶0075) between the interposer substrate (120) and the first semiconductor chip (220);
forming second bumps (432, ¶0097) between the interposer substrate (120) and the second semiconductor chip (420); and
forming an underfill layer (240, ¶0078) between the interposer substrate (120) and the first lower semiconductor chip (220), and between the interposer substrate (120) and the second semiconductor chip (420), encapsulating the first and second bumps (250), wherein the underfill layer (240) extends between a top surface of the first molding layer (150) and a bottom surface of the overhang region of the first lower semiconductor chip (220).
Jang does not disclose “mounting a first semiconductor chip and a second semiconductor chip, horizontally spaced apart from the first semiconductor chip”.
However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art method would not be executed differently if modified to the claimed shape or size. Therefore, the claimed limitations are considered met.
Allowable Subject Matter
Claims 11-18 are allowed.
Regarding claim 11, the prior art does not disclose “removing the carrier substrate to expose the bottom surface of the interposer substrate and the bottom surface of the first molding layer; and performing a thinning process on the interposer substrate and the first molding layer together” in combination with the remaining claimed features
Claims 2, 4-7, 20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the prior art does not disclose “2. The method of claim 1, further comprising grinding the second molding layer to expose a top surface of the first semiconductor chip” in combination with the remaining claimed features.
Regarding claim 4, the prior art does not disclose “forming a first passivation layer on a third surface of the substrate and a fourth surface of the first molding layer, wherein the third surface is opposite to the first surface of the substrate, and wherein the fourth surface is opposite to the second surface of the first molding layer” in combination with the remaining claimed features.
Regarding claim 7, the prior art does not disclose “the first molding layer includes a first dielectric polymer and a plurality of first fillers, the second molding layer includes a second dielectric polymer and a plurality of second fillers, and diameters of each of the second fillers are less than diameters of each of the first fillers” in combination with the remaining claimed features.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM A HARRISTON/ Primary Examiner, Art Unit 2899
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