DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant's arguments filed 12/1/2025 have been fully considered but they are not persuasive.
In response to applicant’s arguments with regard to the independent claim 1 is rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… records a lap for the in-pointer at a slot immediately preceding a slot of the buffer where lap change occurs … records a lap for the out-pointer at a slot immediately preceding a slot of the buffer where lap change occurs …” because Shiue fails to teach a producer paperclip indicator and a consumer paperclip indicator that respectively record a lap for the in-pointer and the out-pointer at a slot immediately preceding the respective lap change in the buffer as Shiue is silent regarding a paperclip-based lap recording mechanism that keeps track of the last known state (i.e. recording a lap at a slot immediately preceding the slot of the buffer); applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, and to further clarify, as Shiue’s flip-flops track when read/write pointer move around FIFO and catches up with write/read pointer (Shiue, col. 5, ll. 1-19), Shiue does teach/suggest flip-flops that track/record last known state of the read pointer and write pointer as the read pointer and write pointer move and lap around FIFO.
As applicant appears to be applying the above arguments for independent claim 1 towards independent claims 10 and 19, the examiner will also apply the above response for independent claim 1 towards independent claims 10 and 19.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… set a consumer flag associated with the consumer entity, the position of the out-pointer, the consumer lap indicator, and the consumer paperclip indicator as equal to a producer flag, the position of the in-pointer, the producer lap indicator, and the producer paperclip indicator, respectively; and restrict the producer entity to write the data until the consumer flag is 0 …” because Graef is silent regarding four different types of indicators and Shiue fails to teach/suggest consumer paperclip indicator and producer paperclip indicator; applicant's arguments have fully been considered, but are not found to be persuasive.
Please note that the features upon which applicant relies (i.e., different types of indicators) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Additionally, by combining Shiue’s set a consumer flag associated with the consumer entity, the position of the out-pointer, the consumer lap indicator, and the consumer paperclip indicator (e.g. equating the consumer flag, the out-pointer, the consumer lap indicator, and the consumer paperclip indicator to flip-flop for read operation) as equal to a producer flag, the position of the in-pointer, the producer lap indicator, and the producer paperclip indicator (e.g. equating the producer flag, the in-pointer, the producer lap indicator, and the producer paperclip indicator to flip-flop for write operation), respectively (e.g. associated with both write pointer flip-flop (41) and read pointer flip-flop (42) being set to logic 1 at the same time: col. 4, ll. 50-54); and the producer entity operating accordingly when the consumer flag is 0 (e.g. associated with write operation operating accordingly when RP flip-flop (42) transition from 1 → 0: col. 5, ll. 1-8) (col. 2, l. 6 to col. 5, l. 29) with Graef’s restrict entity to write the data until (e.g. associated with rejecting write request until sufficient buffer space exist: Fig. 2; col. 5, l. 59 to col. 6, l. 8) (Fig. 1-2; col. 1, l. 54 to col. 2, l. 63; and col. 3, l. 10 to col. 6, l. 8), the resulting combination of the references would teach/suggest the above claimed features.
As applicant appears to be applying the above arguments for independent claim 1 towards independent claims 10 and 19, the examiner will also apply the above response for independent claim 1 towards independent claims 10 and 19.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… wherein the consumer entity operates in parallel with the producer entity …” because Shiue enforces a synchronization discipline in which the read (consumer) path and the write (producer) path cannot operate concurrently ; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, and to further clarify, Shiue does teach/suggest wherein the consumer entity operates in parallel with the producer entity (e.g. associated with read and write operations taking place asynchronously with the FIFO receiving data at any given time for write operation and reading out data at any given time for read operation: col. 2, ll. 61-62; col. 4, ll. 20-49) (col. 2, l. 6 to col. 5, l. 29).
As applicant appears to be applying the above arguments for independent claim 1 towards independent claims 10 and 19, the examiner will also apply the above response for independent claim 1 towards independent claims 10 and 19.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-7, 9-10, 12, 14-16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Graef (US Patent 6,101,329) in view of Shiue (US Patent 5,262,996).
As per claim 1, Graef teaches/suggests a system for data synchronization, comprising: a processor (e.g. associated with processor of computer/electronic devices: col. 3, ll. 36-49); and a memory operatively coupled to the processor, the memory comprising processor-executable instructions which, when executed (e.g. associated with memory with corresponding instruction(s) that is executed by processor in the computer/electronic devices: col. 3, ll. 36-49), cause the processor to: determine a first indicator (e.g. associated with write counter: col. 3, ll. 50-63), associated with a producer entity (e.g. associate with Fig. 1, ref, 10), corresponding to a buffer (e.g. associated with FIFO buffer); determine a second indicator (e.g. associated with read counter: col. 3, l. 64 to col. 4, l. 7) associated with a consumer entity (e.g. associate with Fig. 1, ref, 11); determine a state of the buffer based on the first indicator and the second indicator (e.g. associated with determining how full/empty is the buffer: col. 4, ll. 8-47); in response to a determination of the state of the buffer being full or empty, enable data synchronization based on initial lapping at the buffer (e.g. associated with synchronizing data transferring by blocking reading when buffer is empty or blocking write when buffer is full: col. 4, ll. 8-47); and restrict entity to write the data until (e.g. associated with rejecting write request until sufficient buffer space exist: Fig. 2; col. 5, l. 59 to col. 6, l. 8) (Fig. 1-2; col. 1, l. 54 to col. 2, l. 63; and col. 3, l. 10 to col. 6, l. 8).
Graef does not expressly teach the system for data synchronization, comprising:
a producer lap indicator, wherein the producer lap indicator tracks a lap of an in-pointer around the buffer, wherein the lap of the in-pointer is completed when the in-pointer returns to a corresponding starting point after traversing the buffer;
a consumer lap indicator, wherein the consumer lap indicator tracks a lap of an out-pointer around the buffer, wherein the lap of the out-pointer is completed when the out-pointer returns to a corresponding starting point after traversing the buffer; and
operating with the producer lap indicator and the consumer lap indicator based on paperclipping, wherein to initiate the paperclipping, the processor is configured to:
record a producer paperclip indicator and a consumer paperclip indicator prior to a change in the respective producer lap indicator and the consumer lap indicator associated with the producer entity and the consumer entity,
wherein the producer paperclip indicator records a lap for the in-pointer at a slot immediately preceding a slot of the buffer where lap change occurs, and wherein the consumer paperclip indicator records a lap for the out-pointer at a slot immediately preceding the slot of the buffer, and
determine the state of the buffer based on a comparison between the producer paperclip indicator and the consumer paperclip indicator,
wherein the consumer entity operates in parallel with the producer entity,
wherein the processor is further configured to initiate the paperclipping based on a position of the in-pointer being same as a position of the out-pointer where the lap change occurs; and
operating with the paperclipping;
set a consumer flag associated with the consumer entity, the position of the out-pointer, the consumer lap indicator, and the consumer paperclip indicator as equal to a producer flag, the position of the in-pointer, the producer lap indicator, and the producer paperclip indicator, respectively; and
the producer entity operating accordingly when the consumer flag is 0.
Shiue teaches/suggests a system for data synchronization, comprising: a producer lap indicator (e.g. associated with indicator for write operation including indication regarding which memory section data would be receiving data: col. 2, ll. 6-64), wherein the producer lap indicator tracks a lap of an in-pointer around the buffer, wherein the lap of the in-pointer is completed when the in-pointer returns to a corresponding starting point after traversing the buffer (e.g. associated with tracking a lap being completed during write operation as write pointer moved around FIFO which may indicate full condition as the write pointer catches up to the read pointer: col. 3, ll. 10-26); a consumer lap indicator (e.g. associated with indicator for read operation including indication regarding which memory section would be outputting data: col. 2, ll. 6-64), wherein the consumer lap indicator tracks a lap of an out-pointer around the buffer, wherein the lap of the out-pointer is completed when the out-pointer returns to a corresponding starting point after traversing the buffer (e.g. associated with tracking a lap being completed during write operation as the read pointer moved around FIFO which may indicate empty condition as the read pointer catches up to the write pointer: col. 3, ll. 10-26); and operating with the producer lap indicator and the consumer lap indicator based on paperclipping (e.g. operating with indicator for write operation and read operation based on the state of FIFO that was recorded in corresponding flip-flop), wherein to initiate the paperclipping, the processor is configured to: record a producer paperclip indicator (e.g. associated with flip flop recording indicator for wrote operation) and a consumer paperclip indicator (e.g. associated with flip flop recording indicator for read operation) prior to a change in the respective producer lap indicator and the consumer lap indicator associated with the producer entity and the consumer entity, wherein the producer paperclip indicator records a lap for the in-pointer at a slot immediately preceding a slot of the buffer where lap change occurs, and wherein the consumer paperclip indicator records a lap for the out-pointer at a slot immediately preceding the slot of the buffer (e.g. associated with the collective control sections recording indicators for read and write of FIFO, including for at control section of memory section/slot immediately preceding memory section/slot where lap change occurs), and determine the state of the buffer based on a comparison between the producer paperclip indicator and the consumer paperclip indicator (e.g. associated determining Full or Empty state based on indicators/pointers for read and write), wherein the consumer entity operates in parallel with the producer entity (e.g. associated with read and write operations taking place asynchronously with the FIFO receiving data at any given time for write operation and reading out data at any given time for read operation: col. 2, ll. 61-62; col. 4, ll. 20-49), wherein the processor is further configured to initiate the paperclipping based on a position of the in-pointer being same as a position of the out-pointer where the lap change occurs (e.g. associated with state of pointers for read and write operations being continuously maintained during FIFO operating, including when read/write pointer catching up to write/read pointer); operating with the paperclipping (e.g. associated with the state of the FIFO being recorded in corresponding flip-flop); set a consumer flag associated with the consumer entity, the position of the out-pointer, the consumer lap indicator, and the consumer paperclip indicator (e.g. equating the consumer flag, the out-pointer, the consumer lap indicator, and the consumer paperclip indicator to flip-flop for read operation) as equal to a producer flag, the position of the in-pointer, the producer lap indicator, and the producer paperclip indicator (e.g. equating the producer flag, the in-pointer, the producer lap indicator, and the producer paperclip indicator to flip-flop for write operation), respectively (e.g. associated with both write pointer flip-flop (41) and read pointer flip-flop (42) being set to logic 1 at the same time: col. 4, ll. 50-54); and the producer entity operating accordingly when the consumer flag is 0 (e.g. associated with write operation operating accordingly when RP flip-flop (42) transition from 1 → 0: col. 5, ll. 1-8) (col. 2, l. 6 to col. 5, l. 29).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Shiue’s control architecture into Graef’s storage architecture for the benefit of implementing a simple and efficient architecture (Shiue, col. 3, ll. 27-34) to obtain the invention as specified in claim 1.
As per claim 3, Graef and Shiue teach/suggest all the claimed features of claim 1 above, where Graef and Shiue further teach/suggest the system comprising wherein to initiate the lapping, the processor is configured to: determine the position of the in-pointer, associated with the producer entity, corresponding to the buffer (e.g. associated write pointer for write operation); determine the position of the out-pointer associated with the consumer entity (e.g. associated read pointer for write operation); determine the state of the buffer further based on the position of the in-pointer and the position of the out-pointer (e.g. associated with using write pointer and read pointer for determine the state of the buffer); in response to the state of the buffer being full, restrict the producer entity to write data to the buffer, or the consumer entity to read data from the buffer until an item is removed or added respectively, for a predetermined duration of time (e.g. associated with rejecting write operation in response to buffer being full); and in response to the state of the buffer being empty, enable the producer entity to write the data to the buffer at the position of the in-pointer in the buffer, or the consumer entity to read the data from the position of the out-pointer in the buffer (e.g. associate with rejecting read operation in response to buffer being empty) (Graef, Fig. 1-2; col. 1, l. 54 to col. 2, l. 63; col. 3, l. 10 to col. 6, l. 8; and Shiue, Fig. 3-4; col. 2, l. 6 to col. 5, l. 29).
As per claim 5, Graef and Shiue teach/suggest all the claimed features of claim 3 above, where Graef and Shiue further teach/suggest the system comprising wherein in response to the state of the buffer being full, the processor is configured to set the producer flag associated with the producer entity to 1, indicating that the buffer is full (e.g. associated with setting of logic for write pointer flip flop when data is written, wherein it would have been obvious and/or well-known to one of ordinary skilled in the art to set the logic to 1: Shiue, col. 2, ll. 40-54) (Graef, Fig. 1-2; col. 1, l. 54 to col. 2, l. 63; col. 3, l. 10 to col. 6, l. 8; and Shiue, Fig. 3-4; col. 2, l. 6 to col. 5, l. 29).
As per claim 6, Graef and Shiue teach/suggest all the claimed features of claim 5 above, where Graef and Shiue further teach/suggest the system comprising wherein the processor is further configured to: reset the consumer lap indicator and the position of the out-pointer to 0; and set the consumer flag associated with the consumer entity to 1 (Graef, Fig. 1-2; col. 1, l. 54 to col. 2, l. 63; col. 3, l. 10 to col. 6, l. 8; and Shiue, Fig. 3-4; col. 2, l. 6 to col. 5, l. 29), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features for the FIFO buffering architecture.
As per claim 7, Graef and Shiue teach/suggest all the claimed features of claim 6 above, where Graef and Shiue further teach/suggest the system comprising wherein the processor is further configured to: based on the consumer flag being set to 1, reset the producer lap indicator and the position of the in-pointer to 0, and the producer flag to 0; based on the producer flag being set to 0, set the consumer flag to 0 and wait for the data to be written to the buffer; and based on the consumer flag being set to 0, enable the producer entity to write the data to the buffer (Graef, Fig. 1-2; col. 1, l. 54 to col. 2, l. 63; col. 3, l. 10 to col. 6, l. 8; and Shiue, Fig. 3-4; col. 2, l. 6 to col. 5, l. 29), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features for the FIFO buffering architecture.
As per claim 9, Graef and Shiue teach/suggest all the claimed features of claim 1 above, where Graef and Shiue further teach/suggest the system comprising wherein the state of the buffer is empty when the producer lap indicator and the consumer lap indicator are equal and/or the position of an in-pointer is equal to the position of an out-pointer, and wherein the state of the buffer is full when the producer lap indicator and the consumer lap indicator are not equal (Graef, Fig. 1-2; col. 1, l. 54 to col. 2, l. 63; col. 3, l. 10 to col. 6, l. 8; and Shiue, Fig. 3-4; col. 2, l. 6 to col. 5, l. 29), wherein it would have been obvious and/or well-known to one of ordinary skilled in the art to configure corresponding logic level associate with read and write operations in order to proper determine the buffer being full or empty.
As per claims 10, 12, 14-16 and 18, claims 10, 12, 14-16, and 18 are rejected in accordance to the same rational and reasoning as the above rejection of claims 1, 3, 5-7, and 9.
As per claim 19, claim 19 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1.
II. PERTINENT RELATED PRIOR ART
Kreifels (US Patent 4,891,788): discloses FIFO architecture with a Read pointer determining the location in the FIFO for reading information therefrom and a Write pointer for determining the location in the FIFO for writing information thereto. The Read pointer is incremented for each Read operation and the Write pointer is incremented for each Write operation with the Write pointer having a higher value than the Read pointer. Counter circuitry is provided for determining the proximity of the Read pointer to the Write pointer. When the Read and Write pointer are separated by a predetermined distance that is less than full and greater than empty, a compare signal is generated at a first logic state. If the compare signal is not generated, the output of the counter circuitry is at a second logic state. When it is determined that the output of the counter circuitry is at a first logic state indicating the presence of the compare signal and the external write signal is received, a set signal is generated. A flag is then placed in a set position. When it is determined that the compare signal is next present, the flag is placed in a reset position
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 February 09, 2026