DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
It is not that there appear to be multiple related filings with different office including KIP JPO and EPO. There also appears to be related office action with cited references which applicant has not supplied. Applicant is reminded of their duty to disclose see MPEP 609.
Response to Amendment
It is noted that there are two separate claim sets one submitted on 10/10/2024 and a later one submitted on 10/16/2024 with no status of the claims. The office assume the correct set of claims are those submitted on 10/16/2024 with 22 claims this is consistent with the Fees submitted on 11/7/2024 paying for 22 claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claims 1 12 recitation of an additional ground is un clear it is unclear if there is to be a first ground beyond the additional.
Further multiple sides lack antecedent basis device does not need 4 sides or opposite sides.
Further recitation of wafer or panel level packaging process is unclear what is and is not a wafer or panel level process further it is unclear how the process is to be used.
Further recitation of forming an additional ground (GND) layer on a part of a fan-out packaging substrate and an additional GND layer formed on a part of the fan-out packaging substrate appears to be inconsistent it is a region to become a fan-out section the redistribution layers cause the structure to fan out. There is no fanout a the time of forming the ground layer.
As to claim 2 13 it is unclear how the GND sea ring or pad relates to the other elements specifically the claim does not require the device comprising a GND seal or pad and does not describe it location if it is part of the package. For claim 2 it is unclear when the step occurs if it is a step.
As to claims 2, 5, 13 and 16 it is unclear what the scope of rebuilt is to is intended to describe. It is unclear if one must build it first and then the steps or action is required.
AS to claim 3 and 14 it is unclear what structure constitutes a wiring line for die-to-die connection or when does a wire meet this specific limitation.
As to claim 5, claim 5 is not an active step and does not limit the method
As to claim 6 and 17 it is unclear how a laser direct imaging method is being applied to perform the action of claim 5 and 16. Claim 6 is also not an active step.
As to claim 8, appears to be inconsistent with the normal meaning of multiple redistribution layer on cannot just repeating the step of forming the first dielectric layer or the step of forming the redistribution layer the are formed by alternating the process. Further it is unclear how the step relates to the rest of the steps of claim 1.
As to claims 9 and 20, applicant has not established any GND planes also for claim 9 it is unclear when this occurs.
As to claim 10 and 21 how does the edge relate to the sides. Also how does the metal seal ring relate to the redistribution deposition the office assumes they are the same material otherwise it could not be formed at the same time.
As to claims 11 and 22 it is unclear in time when the recitation of claim 11 is to occur.
As to claim 11 and 22 it is unclear where the vertical connection portion is locater or where the multiple redistribution is located.
As to claim 19 claim 19 suffers from the same issues of claim 8 further it is unclear what the final device structure is to be.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 7-9, 12-17, and 19-20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lee 20220051996.
a. As to claim 1 and 12, Lee teaches A method of manufacturing a fan-out packaging device (figure 8B and paragraph 20), which is a method of manufacturing a packaging device using a wafer or panel level packaging process( unclear the scope), the method comprising: forming an additional ground (GND) layer on a part of a fan-out packaging substrate (items 200) forming a first dielectric layer having a first via hole on the additional GND layer; (item 210) forming a redistribution layer (RDL) on the first dielectric layer and the first via hole (item 252 on 200 and the 256 over 200 9 and 2F); forming a second dielectric layer having a second via hole on the redistribution layer ((item 412 figure 2G); and forming a bump structure on the second dielectric layer and the second via hole so as to be connected to the redistribution layer (item 422), wherein the additional GND layer is formed in directions toward four sides or at least two opposite sides of a die ( it is formed in all directions it is a three dimensional object but also see figure 1b).
b. As to claims 2 and 13, Applicant does not positively require the device comprises a gnd seal or gnd pad but Lee teaches it is connected to tmg which is ground paragraph 28.
c. As to claims 3 and 14, Lee teaches wherein the additional GND layer comprises a wiring line for die-to-die connection it is connected to the pad item TMG for bonding.
d. As to claims 4 and 15, Lee teaches wherein an insulating layer having an additional via hole is formed between the fan-out packaging substrate and the additional GND layer (topmost item 310 at figure 8a directly on item 200).
e. As to claims 5-6 and 16-17 in so far as definite Lee teaches wherein the additional via hole is connected to a GND pad and a signal pad (200 is connect to TMGG and TMS ground and signal are intended use). The claims do not state rebuilding the additional ground pad or form an additional via hole. Applicant is advised that even if applicant states rebuilding this is unclear what is meant. It is noted claims 16-17 are product by process and even if a method was recited it would not overcome the rejection.
f. As to claims 8 and 19, Lee forms at least a top RDL above the bottom thus the step of the step of forming the redistribution layer is repeated.
g. As to claim 9 and 20, recitation of GND layer or plane is intended use Lee teaches the structure otherwise claimed thus Lee teaches wherein the additional GND layer is connected to each or all of GND planes formed at a subsequent redistribution layer
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee.
a. As to claims 7 and 18, Lee does not explicitly teach wherein the insulating layer is formed so as to have a thickness of 2 μm or less.
However, thickness for insulating layer of 2 μm or less were known for packaging and RDL layer.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the layer 310a to be of 2 μm or less to use conventional material sizes to provide expected results of adequate isolation between layers.
Claim(s) 10-11 and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Yang 8624359.
As to claim 10 and 21, Lee does not teach the step of forming the redistribution layer, a sealed type metal sealing ring is formed around an edge of the fan-out packaging substrate to provide an additional conductor path
Yang teaches forming a metal seal item 80 and item 80T in a rerouting layer (figure 1A).
The WLCSP 10 has a chip area 10A defined by a broken line A, and a fan-out area 10B surrounding the chip area 10A. The WLCSP 10 comprises the molded semiconductor device 20, a re-routing laminated structure 40, a plurality of solder balls 60, and a seal ring structure 80. The molded semiconductor device 20 includes a semiconductor device 22 positioned in the chip area 10A, and a mold 26 surrounding the semiconductor device 22 in the fan-out area 10B. The semiconductor device 22 includes an active surface 22A having a plurality of contact pads 24, side surfaces 22S, and a bottom surface 22B. The mold 26 covers the side surfaces 22S and the bottom surface 22B of the semiconductor device 22. The mold 26 has a top surface 26T extending around the active surface 22A of the semiconductor device 22.
Stating:
In order to protect the semiconductor device 22 and the RDL structures, the seal ring structure 80 is formed within and on the re-routing laminated structure 40. The seal ring structure 80 has a top surface 80T exposed to the outside of the re-routing laminated structure 40. The seal ring structure 80 extends around the upper periphery of the semiconductor device 22 over the molded semiconductor device 20. In some embodiments, the seal ring structure 80 extends within the fan-out area 10B over the mold 26. In some embodiments, the seal ring structure 80 extends from the fan-out area 10B to edge portions of the chip area 10A within the re-routing laminated structure 40. In one or more embodiments, the seal ring structure 80 is formed of at least one of metals or metal alloys. The seal ring structure 80 can stop undesirable moisture and mobile ionic contaminants from penetrating through the re-routing laminated structure 40 and through the side surfaces 22S of the semiconductor device 22 into a functional circuit area of the semiconductor device 22, and can enable structural reinforcement of the WLCSP 10, thereby preventing operational reliability of the semiconductor device 22 from being degraded.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form a metal seal ring to prevent moisture and ionic contaminant from intruding and damaging the device.
b. As to claim 11 and 22, Yang does not explicitly teach wherein the sealed type metal sealing ring is connected to the additional GND layer via a vertical connection portion, or when a multiple redistribution layer/dielectric layer structure is formed, the sealed type metal sealing ring is connected to a lower-layer sealed type metal sealing ring via the vertical connection portion and is connected to the additional GND layer via the vertical connection portion.
However, Yang teaches The semiconductor device 22 is obtained by a series of processes including a process of simultaneously fabricating a plurality of integrated circuits on a wafer, a process of sawing the wafer into individual chips constituting the semiconductor device 22. The active surface 22A of the semiconductor device 22 is protected by a passivation layer formed during the process of fabricating the plurality of integrated circuits on the wafer. However, the side surfaces 22S of the semiconductor device 22 are not covered by the passivation layer. Therefore, the side surfaces 22S of the semiconductor device 22 may be vulnerable to undesirable moisture and mobile ionic contaminants. For example, moisture penetrated into the interior of the semiconductor device 22 can be trapped in oxide dielectric layers, and thus increase the dielectric constant of the dielectric layers, or increase possibility of crack propagation or delamination caused by the reduction of the mechanical strength of the dielectric layers. Additionally, moisture penetrated into the interior of the semiconductor device 22 can degrade the performance of unit devices such as transistors formed within the semiconductor device 22, or can cause corrosion or short circuit, thereby reducing reliability of the semiconductor device 22 or causing device failure. The mobile ionic contaminants within the semiconductor device 22 can cause threshold voltage instability in complementary metal oxide semiconductor (CMOS) transistors, or change the surface potential of a silicon surface in the vicinity of the ionic contaminants.
Thus, it would have been obvious to connect the ring to same GND as item 220 of Lee to dissipate any undesired charge build up from the ionic contaminants.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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